Search

Jianbai Zhu

age ~73

from Plano, TX

Also known as:
  • Jian Zhu
  • Jian Bai Zhu
  • I Zhu
  • Zhu Jain
2421 Cimmaron Dr, Plano, TX 750259727470514

Jianbai Zhu Phones & Addresses

  • 2421 Cimmaron Dr, Plano, TX 75025 • 9727470514
  • Mc Kinney, TX
  • Little Elm, TX
  • Denton, TX
  • Colton, TX
  • Lubbock, TX
  • Dallas, TX

Us Patents

  • High Density Vertically Stacked Semiconductor Device

    view source
  • US Patent:
    20050173807, Aug 11, 2005
  • Filed:
    Feb 5, 2004
  • Appl. No.:
    10/772709
  • Inventors:
    Jianbai Zhu - Plano TX,
    Ray Harrison - Garland TX,
  • International Classification:
    H01L023/48
  • US Classification:
    257777000
  • Abstract:
    A high density, high speed semiconductor module including a plurality of active semiconductor chip pairs bonded face-to-face. A functional system within the footprint of a single-chip package is provided by vertically stacking flip-chip pairs and interconnecting the chip pairs on a substrate or package. Assembly of the device including various combinations of more than one chip pair, in combination with individual chips, advantageously utilizes known manufacturing technology and equipment.
  • Laterally Interconnected Ic Packages And Methods

    view source
  • US Patent:
    20080157320, Jul 3, 2008
  • Filed:
    Dec 29, 2006
  • Appl. No.:
    11/617906
  • Inventors:
    Ray D. Harrison - Garland TX,
    Jianbai Zhu - Plano TX,
    Jeffrey J. Wolfe - Sachse TX,
    Frank Stepniak - Dallas TX,
  • International Classification:
    H01L 23/48
    H01L 21/58
  • US Classification:
    257686, 438107, 257E2301, 257E21505
  • Abstract:
    Semiconductor devices and methods for their assembly are described in which IC packages may be combined in novel configurations. A multi-package semiconductor device system and associated methods for its construction include a plurality of packaged semiconductor devices, each provided with at least one lateral electrical contact. The plurality of packaged semiconductor devices so provided are fixed in a coplanar configuration and have the adjacent lateral contacts coupled for operation in concert.
  • Repackaging Semiconductor Ic Devices For Failure Analysis

    view source
  • US Patent:
    6521479, Feb 18, 2003
  • Filed:
    Jan 11, 2002
  • Appl. No.:
    10/044024
  • Inventors:
    Ray D. Harrison - Garland TX
    Jianbai Zhu - Plano TX
    Kendall S. Wills - Sugarland TX
    Willmar Subido - Garland TX
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H01L 2166
  • US Classification:
    438106, 438 14, 438 15, 438459, 438458, 438689, 257778, 257777, 257 29, 257666
  • Abstract:
    The present invention provides a system and method for preparing semiconductor integrated circuits (“ICs”), particularly ball grid arrays (“BGAs”), quad flat packs (“QFPs”) and dual in line packages (“DIPs”) for failure analysis (“FA”) using a variety of techniques, including emission microscopy (“EM”) and externally induced voltage alteration (“XIVA”). This system and method requires precision thinning and polishing of the semiconductor IC device to expose the backside of the die and mounting of the semiconductor device on a secondary package assembly.

Get Report for Jianbai Zhu from Plano, TX, age ~73
Control profile