John H Leshchuk

US Patent:

8598910, Dec 3, 2013

Filed:

Aug 2, 2012

Appl. No.:

13/565083

Inventors:

John Leshchuk - East Hanover NJ, US
Joseph A. Manzella - Macungie PA, US
Walter A. Roper - Lebanon NJ, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03K 19/00
H03K 19/20
H03K 19/094
H03K 5/08
H03L 5/00
H04L 7/00
H04L 25/00
H04L 25/40

US Classification:

326 93, 326112, 326127, 327327, 375371

Abstract:

In described embodiments, a timestamp generator includes a fixed clock domain driven by a fixed frequency clock, a core clock domain, coupled to the fixed clock domain, which is driven by a core clock whose frequency is adjustable during an operation of the timestamp generator. A timestamp logic operating in the core clock domain generates a timestamping output of the timestamp generator. A rate generator operating in both the fixed clock domain and the core clock domain generates per clock cycle increments in the fixed clock domain and transfers carry units from the fixed clock domain into the core clock domain, and a timestamp increment generation of the timestamp logic is clocked by the fixed frequency clock provided by the rate generator. A method for enabling timestamp in an ASIC to be accurate with system clock changes is also described.

US Patent:

50653962, Nov 12, 1991

Filed:

Jan 2, 1990

Appl. No.:

7/460209

Inventors:

James J. Castellano - Freehold NJ
John H. Leshchuk - Tinton Falls NJ
Michael L. Steinberger - Colts Neck NJ

Assignee:

AT&T Bell Laboratories - Murray Hill NJ

International Classification:

H04J 322

US Classification:

370 84

Abstract:

An Inverse Multiplexer is disclosed which first demultiplexes a first data rate input signal into a plurality of second lower data rate subsectional signals, where each subsectional signal is provided with a periodic synchronization marker and includes a data rate which is less than the channel data rate used to transmit that subsectional signal to a remote terminal. Programmable Multiplexers (PMUXs) then operate to each take one or more subsectional signals that are (1) clock synchronized to a PMUX clock, and (2) a rational fraction of the channel data rate, and map contiguously assigned time slots in a capacity domain frame for each subsectional signal to time slots of a time domain frame format using a 2-step or 3-step digit reverse technique. The resultant time domain format has the input subsectional capacity domain time slots substantially uniformly distributed over the time domain frame. At the receiving end, an Inverse Demultiplexer performs the reverse operation to recover the original first data rate input signal.

US Patent:

20190044867, Feb 7, 2019

Filed:

Mar 30, 2018

Appl. No.:

15/942023

Inventors:

- Santa Clara CA, US
Robert Southworth - Chatsworth CA, US
Naru Dames Sundar - Los Gatos CA, US
Yue Yang - Palo Alto CA, US
Charles Michael Atkin - Houston TX, US
John Leshchuk - East Hanover NJ, US

International Classification:

H04L 12/819
H04L 12/26
H04L 12/813

Abstract:

Technologies for controlling jitter at network packet egress at a source computing device include determining a switch time delta as a difference between a present switch time and a previously captured switch time upon receipt of a network packet scheduled for transmission to a target computing device and determining a host scheduler time delta as a difference between a host scheduler timestamp associated with the received network packet and a previously captured host scheduler timestamp. The source computing device is additionally configured to determine an amount of previously captured tokens present in a token bucket, determine whether there are a sufficient number of tokens available in the token bucket to transmit the received packet as a function of the switch time delta, the host scheduler time delta, and the amount of previously captured tokens present in the token bucket, and schedule the received network packet for transmission upon a determination that sufficient tokens in the token bucket.