Jon L Ashburn

US Patent:

6337690, Jan 8, 2002

Filed:

Mar 31, 1999

Appl. No.:

09/283336

Inventors:

Jon L Ashburn - Fort Collins CO
Bryan G Prouty - Wellington CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G09G 539

US Classification:

345531, 345545, 345561

Abstract:

A clear color and count are stored in a frame buffer controller and in a video controller. The image buffer is cleared by writing the clear color into a color bit field and the count into a count bit field of each pixel. For each frame drawn, the count bit field of each pixel modified is updated with the count stored in the frame buffer controller. The counts stored in the frame buffer controller and the video controller are incremented with each new frame. When the counts reach maximum, the process repeats. Each time a pixel is read, the pixels color bit field is replaced with the stored clear color if the pixels count bit field is not equal to the stored count. The color bit field and the count bit field may be part of the same word of frame buffer memory. Or, the count value may be stored in an alpha bit field in lieu of an alpha value. If so, each time a pixel is read by the frame buffer controller, the pixels count bit field may be replaced with a default alpha value stored in the frame buffer controller.

US Patent:

6559852, May 6, 2003

Filed:

Jul 31, 1999

Appl. No.:

09/364972

Inventors:

Jon L Ashburn - Fort Collins CO
Darel N Emmot - Ft Collins CO
Byron A Alcorn - Ft Collins CO

Assignee:

Hewlett Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1328

US Classification:

345533, 345422, 345570, 345503, 710112, 710310

Abstract:

Frame buffer memory bandwidth is conserved by performing a depth comparison between colliding pixels at batch building time. If the incoming pixel fails the depth comparison, then it may be âtossedâ and excluded from any batches currently under construction. The batch building process may then continue without the need for a batch flush responsive to the occurrence of the pixel collision. If the incoming pixel passes the depth comparison, then it may yet be possible to avoid flushing: The current rendering mode of the pipeline is determined. If the current rendering mode does not require read-modify-write operations, then the incoming pixel may be merged with the buffered pixel with which it collides. Merger of the two pixels may be accomplished by overwriting the buffered RGBA pixel components with those of the incoming pixel, but only those components corresponding to asserted bits in the incoming pixels BEN. The buffered BEN may be replaced with the logical OR of the stored BEN and the incoming pixels BEN.

US Patent:

6587112, Jul 1, 2003

Filed:

Jul 10, 2000

Appl. No.:

09/613229

Inventors:

Courtney Goeltzenleuchter - Fort Collins CO
Darel N Emmot - Ft Collins CO
Jon L Ashburn - Fort Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06T 100

US Classification:

345532

Abstract:

A 3D graphics controller configurable to simultaneously copy portions of a pixel region between a back buffer and a front buffer. The 3D graphics controller includes four memory controllers, each controlling a bank of frame buffer memory. A sequence of addresses defining a pixel region is generated. The addresses are distributed to the four memory controllers according to the memory banks (addresses) coupled thereto. Each memory controller is configured to read pixels according to the addresses and a first offset; and write the pixels according to the addresses and a second offset. The offsets are chosen so as not to shift pixels within the banks. Therefore, each memory controller simultaneously and independently copies a portion of the pixel region without accessing any other memory banks resulting in a copy of the entire pixel region.

US Patent:

6628292, Sep 30, 2003

Filed:

Jul 31, 1999

Appl. No.:

09/364973

Inventors:

Jon L Ashburn - Fort Collins CO
Bryan G. Prouty - Wellington CO

Assignee:

Hewlett-Packard Development Company, LP. - Houston TX

International Classification:

G06F 1202

US Classification:

345565, 345570, 345571, 345531, 345533, 710310, 710 39, 710 52

Abstract:

A buffer facilitates reordering of incoming memory access commands so that the memory access commands may be associated automatically according to their row/bank addresses. The storage capacity in the buffer may be dynamically allocated among groups as needed. When the buffer is flushed, groups of memory access commands are selected for flushing whose row/bank addresses are associated, thereby creating page coherency in the flushed memory access commands. Batches of commands may be flushed from the buffer according to a sequence designed to minimize same-bank page changes in frame buffer memory devices. Good candidate groups for flushing may be chosen according to criteria based on the binary bank address for the group, the size of the group, and the age of the group. Groups may be partially flushed. If so, a subsequent flush operation may resume flushing a partially-flushed group when to do so would be more beneficial than flushing a different group chosen solely based on its bank address.

US Patent:

6633298, Oct 14, 2003

Filed:

Jul 31, 1999

Appl. No.:

09/364971

Inventors:

Jon L Ashburn - Fort Collins CO
Bryan G Prouty - Wellington CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1300

US Classification:

345537, 345545, 345570

Abstract:

A buffer facilitates reordering of memory access commands in a memory access command stream so as to create column coherencies that may be exploited with burst-mode memory cycles. A multi-column data storage buffer is provided. Storage control circuitry stores data associated with a memory access command into the multi-column data storage buffer at a column that corresponds to at least one of the LSBs of the column address associated with the memory access command. Flush control circuitry flushes the data storage buffer, when required, in column order. Each entry in the data storage buffer is associated with a unique valid bit. At flush time, the flush control circuitry analyzes the valid bits to determine an appropriate burst type for executing the memory access commands represented by the flushed buffer contents. The flush control circuitry may indicate the determined burst type to memory controller hardware by means of a burst type flag. The data storage buffer may include multiple lines.

US Patent:

6680737, Jan 20, 2004

Filed:

Dec 12, 2002

Appl. No.:

10/317526

Inventors:

Jon L Ashburn - Fort Collins CO
Darel N Emmot - Ft Collins CO
Byron A Alcorn - Ft Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G09G 539

US Classification:

345531, 345533, 345570, 345421, 710 39, 710 54, 710310

Abstract:

Frame buffer memory bandwidth is conserved by performing a depth comparison between colliding pixels at batch building time. If the incoming pixel fails the depth comparison, then it may be âtossedâ and excluded from any batches currently under construction. The batch building process may then continue without the need for a batch flush responsive to the occurrence of the pixel collision. If the incoming pixel passes the depth comparison, then it may yet be possible to avoid flushing: The current rendering mode of the pipeline is determined. If the current rendering mode does not require read-modify-write operations, then the incoming pixel may be merged with the buffered pixel with which it collides. Merger of the two pixels may be accomplished by overwriting the buffered RGBA pixel components with those of the incoming pixel, but only those components corresponding to asserted bits in the incoming pixels BEN. The buffered BEN may be replaced with the logical OR of the stored BEN and the incoming pixels BEN.

US Patent:

6891533, May 10, 2005

Filed:

Apr 11, 2000

Appl. No.:

09/547065

Inventors:

Byron A Alcorn - Ft Collins CO, US
Jon L Ashburn - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06T015/00

US Classification:

345419

Abstract:

Methods and apparatus for compositing separately generated three-dimensional images in a two-dimensional graphics imaging pipeline of a computer graphics system to ultimately render a composited image on a display screen. The computer graphics system includes generally a graphics library and graphics hardware together defining the imaging pipeline, and a graphics application program invoking operations in the imaging pipeline through an application program interface provided by the graphics library. The imaging pipeline may be the only pipeline in the graphics system or it may be part of a larger rendering pipeline that also includes a geometric pipeline that generates two-dimensional images represented by pixel data. The graphics system also includes a frame buffer for storing pixel data to be displayed on the display device. The image compositing module performs depth testing and stencil testing on specific components of the next image that are separately and sequentially processed by the imaging pipeline.

US Patent:

57108790, Jan 20, 1998

Filed:

Jun 8, 1995

Appl. No.:

8/488644

Inventors:

Jon L. Ashburn - Fort Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1500

US Classification:

395141

Abstract:

A quadrilateral is divided into two triangles so that each of the two triangles may then be filled by a triangle fill scan converter. Additionally, the vertices of a triangle are sorted to generate inputs to a fill scan converter. A circuit combines the functions of dividing the quadrilateral into triangles and generating the plane equations for the triangle fill scan converter. Accordingly, similar operations which are performed for both triangles of the quadrilateral may be shared between the plane equations for the two triangles. A circuit also combines the functions of generating the plane equations for any one triangle with automatic sorting of the triangle vertices.