Jon D Trantham

US Patent:

7325155, Jan 29, 2008

Filed:

Sep 14, 2004

Appl. No.:

10/940919

Inventors:

Jon D. Trantham - Chanhassen MN, US
Gina R. Danner - Inver Grove Heights MN, US
Mark A. Heath - Moore OK, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G06F 11/00

US Classification:

714 6

Abstract:

An embedded system with reduced susceptibility to single event upset effects. The system includes an instruction memory that can store at least one instruction set. The instruction memory utilizes a parity checking error-detection scheme. The system also includes a non-volatile memory that can store a copy of the at least one instruction set, and a data memory that can store at least one data sequence. The data memory utilizes an error correction coding (ECC) scheme. A controller, which is responsive to the instruction memory, the non-volatile memory, and the data memory, replaces the at least one instruction set in the instruction memory with the copy of the at least one instruction set from the non-volatile memory, if a parity error is detected in connection with the at least one instruction set in the instruction memory. The controller also operates in conjunction with the data memory to implement the ECC scheme.

US Patent:

8258844, Sep 4, 2012

Filed:

Aug 3, 2006

Appl. No.:

11/498503

Inventors:

Jay Rodger Elrod - Bloomington MN, US
Charles William Thiesfeld - Lakeville MN, US
Jon David Trantham - Chanhassen MN, US

Assignee:

Seagate Technology LLC - Cupertino CA

International Classification:

H03K 3/02

US Classification:

327198, 327142

Abstract:

In general, this disclosure describes techniques for implementing a system-wide reset of multiple devices. The techniques ensure that when any one of the devices of the system is reset, all the devices are reset. For example, a system includes a master reset device and a plurality of slave reset devices that are interconnected by a single reset line to provide improved robustness against electrostatic discharge (ESD) and electromagnetic pulse events. The master reset device detects a reset signal on the reset line and retransmits a true reset signal on the reset line in response to detecting the reset signal. Additionally, the master reset device may enter a blocking state after retransmitting the true reset signal to prevent detecting the reset signal that it transmitted on the reset line to avoid reset lockup.

US Patent:

8468379, Jun 18, 2013

Filed:

Jun 26, 2009

Appl. No.:

12/492951

Inventors:

Jon David Trantham - Chanhassen MN, US

Assignee:

Seagate Technology LLC - Cupertino CA

International Classification:

G06F 1/30
G06F 1/26
G06F 13/00

US Classification:

713340, 713300, 711100

Abstract:

In one embodiment, a solid-state drive contains a plurality of data memory devices requiring elevated voltages for erasure and programming operations. A common voltage regulator, external to the data memory devices, provides the elevated voltage, thereby reducing the overall power consumption of the data storage device.

US Patent:

8479032, Jul 2, 2013

Filed:

Jun 26, 2009

Appl. No.:

12/492935

Inventors:

Jon David Trantham - Chanhassen MN, US
Darren Edward Johnston - Burnsville MN, US
Dean Clark Wilson - Lonsdale MN, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G06F 1/30
G06F 1/16
G06F 13/00

US Classification:

713340, 713300, 711100

Abstract:

Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, a data-storage device is implemented having a memory control circuit controlling nonvolatile and volatile memory. An operating power circuit carries primary-operating power from the host-system to the memories and control circuitry. A backup power circuit includes energy-storage circuitry with one or more energy storage devices. An isolation-regulation circuit provides voltage regulation of power from the host-system and also isolates the host-system provided power from the energy storage devices. A regulation power circuit carries the regulated power from the isolation-regulation circuit to the energy storage devices.

US Patent:

8504860, Aug 6, 2013

Filed:

Jun 26, 2009

Appl. No.:

12/493025

Inventors:

Jon David Trantham - Chanhassen MN, US
Christopher Thomas Cole - Bloomington MN, US

Assignee:

Seagate Technology LLC - Cupertino CA

International Classification:

G06F 1/00
G06F 1/26

US Classification:

713340, 713300

Abstract:

Power is routed from one or more power supplies. As consistent with one or more example embodiments, a data storage device senses and/or is informed of the availability and voltage level of one or more power supplies. Based upon the availability and voltage level of power supplies, circuits in the memory device are powered using one or more of the sensed power supplies. In some applications, the power is drawn in a manner that emulates the behavior of one or more circuits that are respectively powered.

US Patent:

7363564, Apr 22, 2008

Filed:

Jul 15, 2005

Appl. No.:

11/182291

Inventors:

Robert Wayne Moss - Longmont CO, US
Monty Aaron Forehand - Loveland CO, US
Laszlo Hars - Cranberry Township PA, US
Donald Rozinak Beaver - Pittsburgh PA, US
Charles William Thiesfeld - Lakeville MN, US
Jon David Trantham - Chanhassen MN, US
William Preston Goodwill - Edmond OK, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G01R 31/28
H03K 19/00

US Classification:

714734, 714727, 714724, 714726, 714723, 326 8, 326 16, 713182, 726 26

Abstract:

An apparatus comprises at least one port for coupling signals to the apparatus, a mode selector for setting the apparatus to a normal mode or a debug mode, and a port control for controlling access to secure information in the apparatus through the port in accordance with the selected mode. A method for controlling access to the port is also provided.

US Patent:

20040015653, Jan 22, 2004

Filed:

Dec 20, 2002

Appl. No.:

10/327543

Inventors:

Jon Trantham - Chanhassen MN, US

International Classification:

G06F012/00

US Classification:

711/113000, 711/112000

Abstract:

A method of determining an order of execution of a plurality of queued commands in a data storage system includes the step of determining a execution path metrics for each of a plurality of commands in a waiting queue. Each execution path metrics is determined both as a function of an access time between a last command in a ready queue and the associated command in the waiting queue, and as a function of an access time between the associated one of the commands in the waiting queue and another of the commands in the waiting queue. Based upon the determined execution path metrics, one of the commands in the waiting queue is selected and moved from the waiting queue to the ready queue. Also disclosed is a data storage system configured to implement the method.

US Patent:

20060133607, Jun 22, 2006

Filed:

Dec 22, 2004

Appl. No.:

11/021875

Inventors:

Monty Forehand - Loveland CO, US
Jon Trantham - Chanhassen MN, US
Laszlo Hars - Cranberry Township PA, US
Charles Thiesfeld - Lakeville MN, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

H04L 9/00

US Classification:

380044000

Abstract:

An apparatus comprises a circuit for generating a secret root key having bits representative of threshold voltages, and an error correction module for correcting errors in bits of the secret root key to produce a corrected secret root key. A method of generating a secret root key and a data storage system that includes a secret root key are also described.