Jonathan K Choy

US Patent:

20120278591, Nov 1, 2012

Filed:

Apr 27, 2011

Appl. No.:

13/095630

Inventors:

Scott HILKER - San Jose CA, US
Kevin HURD - Ft. Collins CO, US
Mark GIBSON - Timnath CO, US
Jonathan CHOY - Sunnyvale CA, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 9/30

US Classification:

712208, 712E09028

Abstract:

A microprocessor is provided that has a datapath that is split into upper and lower portions. The microprocessor includes a centralized crossbar switch module having a single data movement module. The data movement module is capable of processing instructions that require operands to be exchanged between upper and lower 64-bit halves of the split architecture. The data movement module can access and process all instructions that require simultaneous access to the entire register contents of the upper and lower portions. The data movement module is configured to execute any one of a number of different instructions to perform data manipulation with respect to one or more “split-operands” (also referred to simply as “operands” herein). The data movement module can exchange data (bytes and/or bits) of operands for the upper and lower 64-bit halves so that bytes and/or bits of operands can be moved or rearranged to other positions during execution of a particular instruction. The data movement module can allow for various types of operand data movement/manipulation that may be required to implement instruction processing that may be required per various instructions, such as permute, pack, shuffle, vectored conditional move, extract, shift, rotate instructions, any other instruction in which operand data is manipulated, shifted, moved, re-ordered, shuffled or scrambled.

US Patent:

20100318771, Dec 16, 2010

Filed:

Jun 11, 2009

Appl. No.:

12/482974

Inventors:

Ranganathan Sudhakar - Santa Clara CA, US
Jonathan Choy - Sunnyvale CA, US
Debjit Das Sarma - San Jose CA, US

International Classification:

G06F 9/06
G06F 9/302
G06F 9/315

US Classification:

712221, 712300, 712E09034, 712E09017

Abstract:

A processor includes a decode unit and a byte permute unit. The byte permute unit receives an instruction from the decode unit. The byte permute unit determines whether the instruction corresponds to a shuffle instruction or a shift instruction. For a shuffle instruction, the byte permute unit uses a byte shuffler to perform a shuffle operation indicated by the instruction. For a shift instruction that indicates a shift magnitude, the byte permute unit uses the byte shuffler to byte-level shift a source operand corresponding to the instruction by an integer number of bytes. The byte permute unit also generates a sequence of output bits by bit-shifting the byte-level shifted source operand by a number of bits such that the sum of the number of bits and the integer number of bytes is equal to the shift magnitude.

US Patent:

20140323464, Oct 30, 2014

Filed:

May 16, 2012

Appl. No.:

14/118541

Inventors:

- Menlo Park CA, US
- Oakland CA, US
David Michael Goldstein - Redwood City CA, US
Jesse Mcfarland - Oakland CA, US
Shyam Krishnan - San Francisco CA, US
Jonathan Choy - Lafayette CA, US

International Classification:

C07D 487/04
C07D 471/04
C07D 403/12
C07D 401/12
C07D 401/14
C07D 239/48
C07D 239/94

US Classification:

51421018, 5142358, 51425218, 5142591, 5142621, 51426411, 5142664, 514275, 544122, 544262, 544279, 544281, 544293, 544323, 544324

Abstract:

Provided herein are kinase inhibiting compounds and methods of using the same.