Justin Michael Schauer

US Patent:

7636361, Dec 22, 2009

Filed:

Sep 27, 2005

Appl. No.:

11/242113

Inventors:

Jo C. Ebergen - San Francisco CA, US
Justin M. Schauer - Palo Alto CA, US
Robert D. Hopkins - Hayward CA, US
Ivan E. Sutherland - Santa Monica CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H04L 12/28

US Classification:

3703954, 370236

Abstract:

One embodiment of the present invention provides a system that asynchronously controls sending data items from a sender to a receiver. This system includes a set of sending FIFOs, a set of receiving FIFOs, as well as a shared data path between the sender and the receiver. The system also includes a set of control paths that operate in parallel between the sender and the receiver, wherein a given control path controls the transmission of data items between a corresponding sending FIFO and a corresponding receiving FIFO through the shared data path. The system further includes a round-robin scheduling mechanism which activates one control path at a time in a predetermined sequence. An activated control path asynchronously controls the sending of a data item from a corresponding sending FIFO to a corresponding receiving FIFO. By operating the control paths in parallel in the predetermined sequence, the system does not have to wait a request-acknowledge cycle time between the sender and the receiver before sending consecutive data items through the shared data path, but can instead send multiple data items through the shared data path within a single request-acknowledge cycle time.

US Patent:

7649255, Jan 19, 2010

Filed:

Dec 6, 2006

Appl. No.:

11/635336

Inventors:

Alex Chow - East Palo Alto CA, US
Robert D. Hopkins - Hayward CA, US
Justin M. Schauer - Palo Alto CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H01L 23/34
H01L 23/48

US Classification:

257723, 257773, 257786, 257777, 257E23144, 438 14, 438381

Abstract:

A semiconductor die includes proximity connectors proximate to a surface of the semiconductor die. This semiconductor die is configured to communicate signals with another semiconductor die via proximity communication through one or more of the proximity connectors. In particular, the proximity connectors include a first group of proximity connectors that is configured to facilitate determining a first separation between the semiconductor die and the other semiconductor die by comparing coupling capacitances between the semiconductor die and the other semiconductor die. Note that the first group of proximity connectors includes a first proximity connector and a second proximity connector, and the second proximity connector at least partially encloses an in-plane outer edge of the first proximity connector.

US Patent:

7750709, Jul 6, 2010

Filed:

Jan 5, 2007

Appl. No.:

11/651221

Inventors:

Justin M. Schauer - San Francisco CA, US
Robert D. Hopkins - Hayward CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

H03H 11/26

US Classification:

327264, 327261, 327268, 327276, 327277, 327278, 438141, 438142

Abstract:

One embodiment of the present invention provides a system that biases a floating node within an integrated circuit. During operation, the system first identifies the floating node within the integrated circuit to be biased. The system then determines a desired bias voltage. Next, the system couples a low-power bias source to the floating node to supply the desired bias voltage, wherein the floating node is biased without stopping data transmission through the floating node during biasing.

US Patent:

7871833, Jan 18, 2011

Filed:

Nov 9, 2009

Appl. No.:

12/615116

Inventors:

Alex Chow - East Palo Alto CA, US
Robert D. Hopkins - Hayward CA, US
Justin M. Schauer - San Francisco CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

H01L 21/00
H01L 21/66

US Classification:

438 14, 438 10, 438107, 257E21521

Abstract:

A semiconductor die includes proximity connectors proximate to a surface of the semiconductor die. This semiconductor die is configured to communicate signals with another semiconductor die via proximity communication through one or more of the proximity connectors. In particular, the proximity connectors include a first group of proximity connectors that is configured to facilitate determining a first separation between the semiconductor die and the other semiconductor die by comparing coupling capacitances between the semiconductor die and the other semiconductor die. Note that the first group of proximity connectors includes a first proximity connector and a second proximity connector, and the second proximity connector at least partially encloses an in-plane outer edge of the first proximity connector.

US Patent:

7979754, Jul 12, 2011

Filed:

Jan 12, 2009

Appl. No.:

12/352488

Inventors:

Robert J. Drost - Los Altos CA, US
Ronald Ho - Mountain View CA, US
Justin M. Schauer - San Francisco CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G06F 11/00

US Classification:

714704, 714 30, 714 25, 714712, 714715, 714724, 714733, 714734, 714745, 714 47, 714700, 327 51, 327199, 327201, 324500, 438107, 29834, 385 14, 375256, 700114

Abstract:

A method of testing a proximity communication system for voltage margin by impressing a voltage upon the data link between the transmitter on one chip and the receiver on the other chip coupled to the transmitter through a capacitively coupling circuit formed by juxtaposed capacitor pads on the respective two chips. The impressed voltage is varied and the output of the receiver is monitored to determine an operational voltage margin. The floating inputs on the receiver may be continuously biased by connecting them to variable biasing supply voltages through high impedances. When the floating inputs are periodically refreshed to a refresh voltage during a quiescent data period, the refresh voltage is varied between successive refresh cycles. The variable test voltage may be applied to transmitter output when it is in a high-impedance state, and the output of the receiver is measured.

US Patent:

8644759, Feb 4, 2014

Filed:

Jan 6, 2009

Appl. No.:

12/349011

Inventors:

Justin M. Schauer - San Francisco CA, US
Robert David Hopkins - Hayward CA, US
Robert J. Drost - Los Altos CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

H04B 5/00

US Classification:

455 411, 36518532, 36518521, 330253, 330288, 330261, 330277, 257369, 257290, 257314, 257323, 257319

Abstract:

Offset voltages developed on floating nodes on inputs to high-performance amplifiers that are DC isolated from the data signals input to amplifiers are cancelled by connecting a highly resistive element between the input node and a predetermined potential, particularly useful in proximity communication systems in which two chips are connected through capacitive or inductive coupling circuits formed jointly in the two chips. The resistive element may be an off MOS transistor connected between the node and a desired bias voltage or a MOS transistor with its gate and drain connected to the potential. Multiple bias voltages may be distributed to all receivers and locally selected by a multiplexer for application to one or two input nodes of the receiver. The receiver output can also serve as a predetermined potential when the resistive element has a long time constant compared to the data rate or the resistive element is non-linear.

US Patent:

20080061801, Mar 13, 2008

Filed:

Aug 23, 2006

Appl. No.:

11/509246

Inventors:

Alex Chow - East Palo Alto CA, US
Robert D. Hopkins - Hayward CA, US
Justin M. Schauer - Palo Alto CA, US

International Classification:

G01R 27/26

US Classification:

324681

Abstract:

In a method for determining capacitance, a first time-varying signal is driven on a first terminal of a first capacitor and a second time-varying signal is driven on a first terminal of a second capacitor, where the first time-varying signal and the second time-varying signal have a pre-determined phase relationship with each other.These signals are received on second terminals of the first capacitor and the second capacitor and demodulated using a periodic signal to produce demodulated signals. This periodic signal has the same fundamental frequency as the first time-varying signal and the second time-varying signal. A DC component in the demodulated signals is then determined by filtering the demodulated signals, and the sign of the DC component is used to determine a relative capacitance of the first capacitor and the second capacitor.

US Patent:

20140052713, Feb 20, 2014

Filed:

Aug 20, 2012

Appl. No.:

13/590110

Inventors:

Justin Schauer - San Francisco CA, US
Philip Amberg - San Jose CA, US

International Classification:

G06F 17/30

US Classification:

707722, 707E17082

Abstract:

Techniques are described for performing grouping and aggregation operations. In an embodiment, a request is received to aggregate data grouped by a first column. In response to receiving the request, values are loaded from the first column into an input cache. The values include values, from the first column, from a set of rows. A filter unit is programmed with logic to perform a comparison between a particular value, from the first column of a first row, and values in the first column of a plurality of rows, of the set of rows. Based on the comparison, a predicate result is generated that identifies rows, within the plurality of rows, that have a valued in the first column that matches the particular value. An aggregate value for a second column is generated by aggregating values, from the second column, of each of the rows identified by the predicate result.