Keith Truong - San Jose CA, US John Schadt - Bethlehem PA, US Ravi Lall - Portland OR, US William Andrews - Macungie PA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K 19/094
US Classification:
326 83, 326 68, 327333
Abstract:
In one embodiment of the invention, a programmable device, such as an FPGA, has a programmable input buffer with a VCCIO-powered buffer stage for high-voltage signaling and a VCC-powered buffer stage for low-voltage signaling. In addition to a main driver section, the VCCIO-powered buffer stage has a mixed-mode section for handling multiple different over-drive and multiple different under-drive conditions, a hysteresis section for providing multiple different trip-point hysteresis modes of operation, and a level-shifting section with look-ahead circuitry that enables the main driver section to be implemented with low-power, high-threshold devices, while still enabling the VCCIO-powered buffer stage to operate with low skew and high speed.
Hysteresis Control Systems And Methods For Programmable Logic Devices
Various techniques are provided to implement hysteresis control for programmable logic devices (PLDs). In one example, a PLD includes a hysteresis control circuit configured to generate a hysteresis control signal based on a core voltage and an input/output (I/O) voltage. The PLD further includes an I/O cell associated with an I/O fabric of the PLD and powered by the I/O voltage. The I/O cell includes a first buffer circuit configured to receive an input voltage and generate a first buffer voltage based on the input voltage. The I/O cell further includes a hysteresis generator configured to generate a hysteresis voltage based on the hysteresis control signal and the I/O voltage. The I/O cell further includes a second buffer circuit configured to generate a second buffer voltage based on the first buffer voltage and the hysteresis voltage. Related methods and systems are provided.
Amd Jun 1998 - May 1999
Graduate Rotation Engineer
Lattice Semiconductor Jun 1998 - May 1999
Staff Design Engineer
Education:
University of California
Northeastern University
Doctorates, Doctor of Education, Education, Organizational Leadership
University of California, Berkeley
Bachelors, Bachelor of Science, Electrical Engineering, Electrical Engineering and Computer Science, Computer Science
Skills:
Verilog Circuit Design Fpga Semiconductors Debugging Integrated Circuit Design Cadence Eda Simulations Analog Soc Embedded Systems Ip Ic Cmos Spice Io Design Analog Circuit Design Logic Design Vlsi Esd Design Floorplanning Integrated Circuits Field Programmable Gate Arrays
Interests:
Social Services Children  Hiking and Biking Meditation and Yoga Education Environment  Music Appreciation Poverty Alleviation  Meditation and Yoga Hiking and Biking Philosophy and Spirituality Disaster and Humanitarian Relief Health Music Appreciation