Ken Chi Pham

US Patent:

6595699, Jul 22, 2003

Filed:

Aug 3, 2001

Appl. No.:

09/922946

Inventors:

Luu Thanh Nguyen - Sunnyvale CA
Ken Pham - San Jose CA
Peter Deane - Los Altos CA
William Paul Mazotti - San Martin CA
Bruce Carlton Roberts - San Jose CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G02B 636

US Classification:

385 88, 385 89, 385 90, 385 92, 385 14

Abstract:

An optoelectronic component is described that includes a photonic device carried by a substrate. A support structure having a relatively higher portion and a relatively lower portion is formed on or attached to the substrate. In a preferred embodiment, the support structure is a dam structure formed by dispensing a flowable material onto the substrate and hardening the dispensed material. The optoelectronic component further includes one or more optical fibers, with each optical fiber being in optical communication with an active facet on the photonic device. The relatively higher and lower portions of the support structure are arranged to position the optical fiber(s) at a desired standoff distance from the photonic device and to slightly incline the distal tip of each optical fiber relative to the top surface of the photonic device. The described packaging approach can be used in both single fiber and multi-channel devices. In some specific embodiments, the support structure is arranged to engage a fiber termination that holds the optical fiber(s).

US Patent:

6624507, Sep 23, 2003

Filed:

Aug 3, 2001

Appl. No.:

09/922358

Inventors:

Luu Thanh Nguyen - Sunnyvale CA
Ken Pham - San Jose CA
Peter Deane - Los Altos CA
William P. Mazotti - San Martin CA
Bruce C. Roberts - San Jose CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 2302

US Classification:

257686, 257777

Abstract:

The present invention pertains to using a leadless leadframe package as the semiconductor device package component of an opto-electronic combinational device. Leadless leadframe packages (LLPs) have very small form factors that allow an opto-electronic device to also have a small overall form factor.

US Patent:

6628000, Sep 30, 2003

Filed:

Nov 19, 2001

Appl. No.:

10/006443

Inventors:

Ken Pham - San Jose CA
Jia Liu - San Jose CA
Luu Thanh Nguyen - Sunnyvale CA
William Paul Mazotti - San Martin CA
Bruce Carlton Roberts - San Jose CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 23544

US Classification:

257797, 257666, 257432, 438 65, 438111

Abstract:

Techniques for maintaining the optical coupling efficiency between photonic devices of an optoelectronic module and its interconnecting optical fibers are described. The techniques ensure that the mating surfaces of an optical sub-assembly and a chip sub-assembly remain planar to each other throughout and after the soldering process of the optoelectronic manufacturing process. These techniques include the use of a ceramic fixture made of a stack of plates having openings that secure the orientation of the optical and chip sub-assemblies. The fixture can have one or more openings to secure a respective one or more combination of optical and chip sub-assemblies. A high temperature tape can also be used to maintain the parallelism between the optical and chip sub-assemblies. An optical sub-assembly having pedestals on its bottom surface can also be use to maintain parallelism of the optical and chip sub-assemblies. Methods of using each technique is also described.

US Patent:

6642613, Nov 4, 2003

Filed:

Sep 4, 2001

Appl. No.:

09/947210

Inventors:

Luu Thanh Nguyen - Sunnyvale CA
Ken Pham - San Jose CA
Peter Deane - Los Altos CA
William Paul Mazotti - San Martin CA
Bruce Carlton Roberts - San Jose CA
Jia Liu - San Jose CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 2302

US Classification:

257686, 257777

Abstract:

The present invention provides a technique for manufacturing a low cost device that provides a true die to external fiber optic connection. Specifically, the present invention relates to several techniques for joining an optical device package to a semiconductor device package. The first technique involves using wirebond studs and an adhesive material, the second technique involves the use of an anisotropic conductive film, and the third technique involves the use of solder material. Each of these techniques provides high levels of thermal, electrical and optical performance. The methods apply to optical sub-assembly and chip sub-assembly interfaces in transceivers, transmitters, as well as receivers for opto-electronic packages.

US Patent:

6655854, Dec 2, 2003

Filed:

Aug 3, 2001

Appl. No.:

09/922357

Inventors:

Luu Thanh Nguyen - Sunnyvale CA
Ken Pham - San Jose CA
Peter Deane - Los Altos CA
William Paul Mazotti - San Martin CA
Bruce Carlton Roberts - San Jose CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G02B 636

US Classification:

385 88, 385 49, 385 92, 438 26, 438 27, 438 29

Abstract:

An optoelectronic component is described that includes a photonic device carried by a base substrate. A dam structure is formed on the base substrate by dispensing and hardening a precise amount of a flowable material. The dam structure is sized to define a desired standoff between an optical fiber and an active facet on the photonic device. In embodiments where the photonic device is wire bonded to the base substrate, it may be desirable to provide a reverse wire bond in order to permit the optical fiber to be placed closer to the photonic device. In some embodiments, the base substrate takes the form of a flexible material having electrically conductive traces thereon that are electrically connected to the photonic device. An optical component support block may be provided to support the flex material. In some implementations, a semiconductor die may be directly soldered to the traces on the flexible material.

US Patent:

6730170, May 4, 2004

Filed:

Nov 17, 2000

Appl. No.:

09/715358

Inventors:

Ken Pham - San Jose CA
Nikhil Vishwanath Kelkar - San Jose CA
Vivek Kishorechand Arora - Mountain View CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

B05C 300

US Classification:

118406, 118504

Abstract:

An encapsulant applicator comprising a flexor formed of a resilient material and a substantially rigid blade is described. The blade is attached to the flexor in a way that during a smoothing process, a force applied through the flexor is distributed across the second edge of the blade. Another aspect of the invention pertains to a system for forming a substantially uniform layer of material on a surface of a semiconductor wafer. The system of the present invention includes a stencil, an applicator and a conveyor device. The stencil is placed over the surface of the wafer so that an opening in the stencil exposes a portion of the surface of the wafer. The conveyor device is connected to the flexor so that during the smoothing process, the conveyor device moves the applicator across the opening of the stencil. Yet another aspect of the invention pertains to a method for applying a substantially uniform layer of flowable material to a surface of a semiconductor wafer using the applicator as described.

US Patent:

6749345, Jun 15, 2004

Filed:

May 24, 2002

Appl. No.:

10/155743

Inventors:

Stephen Andrew Gee - Danville CA
Luu Thanh Nguyen - Sunnyvale CA
Ken Pham - San Jose CA
Jia Liu - San Jose CA
William Paul Mazotti - San Martin CA
Bruce Carlton Roberts - San Jose CA
Peter Deane - Los Altos CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G02B 638

US Classification:

385 75

Abstract:

Electro-optical packages that embed the electronics of the packages directly to the optical cabling, provide short electrical connection paths for high performance, and that provide a robust interconnects. A first electro-optical package includes an integrated circuit and a connector sleeve configured to receive a plug-in optical assembly from the underside of the PC board. The plug-in optical assembly includes a backing piece and an opto-electric device mounted onto the backing piece. An electrical connection is provided between the opto-electric device and a contact location on the backing piece and a contact is provided between the contact location on the backing piece and the integrated circuit. With a second electro-optical package, an integrated circuit having an active surface facing in a first direction and an opto-electric device having contact points facing a second direction are provided. The integrated circuit and the opto-electric are positioned with respect to one another such that a direct electrical connection can be formed between the active surface of the integrated circuit and the contact points of the opto-electrical device.

US Patent:

6802654, Oct 12, 2004

Filed:

Apr 9, 2002

Appl. No.:

10/119619

Inventors:

Bruce C. Roberts - San Jose CA
Stephen A. Gee - Danville CA
William P. Mazotti - San Martin CA
Luu T. Nguyen - Sunnyvale CA
Jia Liu - San Jose CA
Peter Deane - Los Altos CA
Ken Pham - San Jose CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G02B 636

US Classification:

385 88, 385 92

Abstract:

The invention comprises a connector apparatus for electrically interconnecting a chip sub-assembly to an optical sub-assembly. The apparatus includes a connector sleeve with a chip sub-assembly having at least one electrical connection arranged thereon. The connector sleeve is suitable for receiving a connector plug that includes an optical fiber optically coupled to the photonic devices of an optical sub-assembly that includes electrical connectors. The connector plug is engaged with the connector sleeve, thereby electrically interconnecting the electrical connections of the chip sub-assembly to the electrical connectors of the optical sub-assembly such that electrical signals can pass between the chip sub-assembly and a photonic device of the optical sub-assembly.