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Kent B Waterson

from Hollis Center, ME

Kent Waterson Phones & Addresses

  • 519 Deerwander Rd, Hollis Center, ME 04042 • 2077274255
  • Arlington, TX
  • Fort Worth, TX
  • South Portland, ME
  • Grand Prairie, TX

Us Patents

  • Apparatus And Method For Initializing A Universal Serial Bus Device

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  • US Patent:
    6353866, Mar 5, 2002
  • Filed:
    Jan 7, 1998
  • Appl. No.:
    09/003925
  • Inventors:
    David J. Fensore - New Gloucester ME
    Kent Bruce Waterson - South Portland ME
    Gregory Lewis Dean - Standish ME
    Robert Macomber - Portland ME
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    G06F 1300
  • US Classification:
    710104, 710 8
  • Abstract:
    A method and apparatus for dynamically assigning and enabling a unique functional address for a Universal Serial Bus device. A host assigns the unique functional address during a control transaction. The Universal Serial Bus device disables the default address and enables the unique functional address during a status stage of the control transaction to avoid an error window.
  • Apparatus And Method For Initializing A Universal Serial Bus Device

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  • US Patent:
    6415343, Jul 2, 2002
  • Filed:
    Sep 19, 2001
  • Appl. No.:
    09/955618
  • Inventors:
    David J. Fensore - New Gloucester ME
    Kent Bruce Waterson - South Portland ME
    Gregory Lewis Dean - Standish ME
    Robert Macomber - Portland ME
  • Assignee:
    National Semicondoctor Corporation - Santa Clara CA
  • International Classification:
    G06F 1300
  • US Classification:
    710104, 710 9
  • Abstract:
    A method and apparatus for dynamically assigning and enabling a unique functional address for a Universal Serial Bus device. A host assigns the unique functional address during a control transaction. The Universal Serial Bus device disables the default address and enables the unique functional address during a status stage of the control transaction to avoid an error window.
  • Integrated Circuit With Test Signal Buses And Test Control Circuits

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  • US Patent:
    55419356, Jul 30, 1996
  • Filed:
    May 26, 1995
  • Appl. No.:
    8/450726
  • Inventors:
    Kent B. Waterson - Everman TX
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    G06F 1100
  • US Classification:
    371 225
  • Abstract:
    An integrated circuit (IC) with multiple input-only, output-only and combination input/output terminals which can be functionally tested at both the IC and circuit board levels includes programmably-designated, internal test signal buses for allowing functional tests to be performed upon portions of the IC not normally accessible via its outside terminals. Programmably-controlled signal switches allow input and output test signals to be routed directly to and from those functional areas of the IC sought to be tested. Further included are a logic circuit for logically ANDing all of the input signals and programmably-controlled output signal buffers for selectively driving each output terminal to a logic zero, logic one or high impedance state, thereby allowing tests to be conducted to ensure that the various input and output terminals are not electrically shorted to one another or circuit ground.
  • Apparatus And Method For Handling Universal Serial Bus Control Transfers

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  • US Patent:
    62055011, Mar 20, 2001
  • Filed:
    Jan 7, 1998
  • Appl. No.:
    9/004002
  • Inventors:
    David Brief - Ra'anana, IL
    David J. Fensore - New Gloucester ME
    Kent Bruce Waterson - South Portland ME
    Gregory Lewis Dean - Standish ME
  • Assignee:
    National Semiconductor Corp. - Santa Clara CA
  • International Classification:
    G06F 1300
  • US Classification:
    710100
  • Abstract:
    A method and apparatus for performing a control transfer on a Universal Serial Bus (USB) device. A USB device includes a memory space for reading and writing data transmitted over a USB network. The memory space is shared between a plurality of endpoints. A host initiates a control transfer by transmitting a SETUP token to a first endpoint. The endpoint must accept the SETUP token. If the first endpoint does not expect the SETUP token, or if another endpoint is active, the device stores the token until a buffer is allocated and the first endpoint is made active.
  • Integrated Circuit With Multiple Functions Sharing Multiple Internal Signal Buses According To Distributed Bus Access And Control Arbitration

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  • US Patent:
    57746842, Jun 30, 1998
  • Filed:
    Oct 8, 1996
  • Appl. No.:
    8/730996
  • Inventors:
    Ralph Warren Haines - Atherton CA
    Dan Craig O'Neill - San Carlos CA
    Stephen C. Pries - Grand Prairie TX
    William V. Miller - Arlington TX
    Kent B. Waterson - Everman TX
    David S. Weinman - Dallas TX
    Michael J. Shay - Arlington TX
    Jianhua Helen Pang - Arlington TX
    Daniel R. Herrington - Burleson TX
    Brian J. Marley - San Jose CA
    John R. Gunther - Alvarado TX
    Alexander Perez - Suunnyvale CA
    James Andrew Colgan - Ichikawa, JP
    Robert James Divivier - San Jose CA
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01J 1300
  • US Classification:
    395309
  • Abstract:
    An integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared among three tiers of internal circuit functions: a central processing unit and a DMA controller; a DRAM controller and a bus interface unit; and peripheral interface circuits, such as PCMCIA and display controllers. Two of the physical buses correspond to two of the logical buses and are used for communications within the IC. The third physical bus corresponds to three of the logical buses and is used for communications between the IC and circuits external to the IC. Arbitration for accessing and controlling the various signal buses is distributed both within and among the three tiers of internal circuit functions. Maximum performance is thereby achieved from the circuit functions accessed most frequently, while still achieving high performance from those circuit functions accessed less frequently.
  • Apparatus And Method For Providing An Interface To A Compound Universal Serial Bus Controller

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  • US Patent:
    61579750, Dec 5, 2000
  • Filed:
    Jan 7, 1998
  • Appl. No.:
    9/004005
  • Inventors:
    David Brief - Ra'anana, IL
    Kent Bruce Waterson - South Portland ME
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    G06F 9445
  • US Classification:
    710104
  • Abstract:
    A method and apparatus for providing a programming interface to a Universal Serial Bus Device. The programming interface is partitioned so that an external controller does not handle intermediate transfers such as packet retry, handshake packets or intermediate response to error conditions. The programming model consists of a number of endpoint pipes, each of which can be configured to provide one of several functions.
  • Combination Of Input Output Circuitry And Local Area Network Systems

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  • US Patent:
    57547645, May 19, 1998
  • Filed:
    Feb 22, 1994
  • Appl. No.:
    8/200097
  • Inventors:
    Timothy D. Davis - Arlington TX
    Roman Baker - Sunnyvale CA
    Dan E. Daugherty - Burleson TX
    Martin S. Michael - Los Gatos CA
    Ahmed Masood - Austin TX
    Kent Bruce Waterson - Everman TX
    Hon C. Fung - Arlington TX
    Mark Douglas Koether - Grand Prairie TX
    J. Scott Johnson - Fort Worth TX
  • Assignee:
    National Semiconductor Corp. - Santa Clara CA
  • International Classification:
    G06F 1300
    H04L 1200
  • US Classification:
    39520001
  • Abstract:
    Input/output and local area network functions are combined into a single integrated circuit on a single semiconductor (e. g. , a single piece of silicon). Preferred system embodiments on a single integrated circuit are typically placed inside a host system (e. g. , a personal computer based on Intel. RTM. 's 286, 386, 486, and Pentium microprocessors) and interrelate with standard operating systems (e. g. , Microsoft. RTM. 's DOS, IBM. RTM. 's OS/2) on traditional, commonly used bus architectures (e. g. , Industry Standard Architecture and Enhanced Industry Standard). Local area network circuitry and input and output circuitry are both coupled to at least one host system (and indirectly to potentially any number of host systems tied together via the local area network system) via a common data bus. The input and output circuitry couples the host system to at least one input/output channels. Examples of the types of input/output channels are a first serial interface, a second serial interface, a parallel port, a hard drive, a floppy drive, and/or any combination thereof.

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