Kevin J Blostic

US Patent:

20120216091, Aug 23, 2012

Filed:

Sep 21, 2011

Appl. No.:

13/238382

Inventors:

Kevin Joseph Blostic - Bentleyville PA, US
James Jacob Riling - Pittsburgh PA, US
Adam Edward Szymkowiak - Sewickley PA, US
Todd Anthony DeLong - Ivy VA, US
Joseph William Reutzel - Pittsburgh PA, US

Assignee:

Ansaldo STS USA, Inc. - Pittsburgh PA

International Classification:

G06F 11/00

US Classification:

714741, 714E11144

Abstract:

A method of testing a target electronic device implemented in a configurable integrated circuit device includes receiving a baseline design for the target electronic device in a hardware description language, establishing a fault model for the particular configurable integrated circuit device, synthesizing the fault model in the hardware description language, embedding the synthesized fault model into the baseline design to create a modified baseline design in the hardware description language which enables one or more targeted signals to be selectively corrupted, creating a fault model enabled target device on the particular configurable integrated circuit device using the modified baseline design, performing a number of fault injection experiments on the fault model enabled target device, wherein each fault injection experiment includes causing at least one of the one or more targeted signals to be corrupted within the fault model enabled target device.