Khue D Duong

US Patent:

58804927, Mar 9, 1999

Filed:

Oct 16, 1995

Appl. No.:

8/543532

Inventors:

Khue Duong - San Jose CA
Stephen M. Trimberger - San Jose CA

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H01K 2710

US Classification:

257209

Abstract:

An electrical connection arrangement for a programmable integrated circuit is provided. An electrical device is disposed proximate to a vertical longline which is used for transporting address and data signals. The electrical device includes a vertical address line extending from the device. A horizontally arranged interconnection line is electrically connected to the vertical address line extending from the device. Furthermore, the horizontally arranged interconnection line is programmably connectable to the vertical longline. By electrically hardwire connecting the horizontally arranged interconnection line to the vertical address line extending from the device, only one programmable interconnect point is required to transfer signals from the vertical longline into the electrical device itself. Thus, impedance is reduced, while addressing speed is improved. Also, by adding additional horizontal interconnect lines, the present invention reduces routing barriers.

US Patent:

58150048, Sep 29, 1998

Filed:

Oct 16, 1995

Appl. No.:

8/543591

Inventors:

Stephen M. Trimberger - San Jose CA
Khue Duong - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 738
H03K 19177

US Classification:

326 41

Abstract:

A field programmable gate array having independently buffered output lines of a CLB for handling critical path situations. One of the CLB's output ports is coupled to a vertical interconnect line and a horizontal interconnect line. Two separate buffers are used to drive these lines. One buffer drives the horizontal interconnect line, while the other drives the vertical interconnect line. One of these lines is used to conduct the output signal that corresponds to the critical path. The other line is used to conduct the output signal onto other branches that are not part of the critical path. Hence, by using a separate buffer to drive the critical path, it is not loaded with the circuits associated with the non-critical branches.

US Patent:

58119850, Sep 22, 1998

Filed:

Jan 31, 1997

Appl. No.:

8/783389

Inventors:

Stephen M. Trimberger - San Jose CA
Khue Duong - San Jose CA
Robert O. Conn - Los Gatos CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19173

US Classification:

326 38

Abstract:

A input/output circuit (IOB) within an integrated circuit (IC) device, the output signal driving circuitry of the input/output device contains a dedicated multiplexer on the output path wherein a first and second output signal can be time multiplexed on a single output pad. The multiplexer can also be configured to perform as a high speed gate to realize AND, OR, XOR, and XNOR functions. Within an input/output circuit of a programmable integrated circuit, the system provides a dedicated multiplexer that can select between one of two output signals for sending over the single output pad of the IC device. In lieu of using a programmable memory cell as the select control for the dedicated multiplexer, the system allows a number of lines, including an output clock signal, to be the select control. By using the output clock as the select control, the data signals can be effectively time multiplexed over a single output pad and referenced by the output clock. This output multiplexer circuit effectively doubles the number of output signals the IC device can provide with a given number of output pads.

US Patent:

57125791, Jan 27, 1998

Filed:

Oct 16, 1995

Appl. No.:

8/543693

Inventors:

Khue Duong - San Jose CA
Stephen M. Trimberger - San Jose CA
Robert O. Conn - Los Gatos CA
John E. Mahoney - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19177
H03K 1900

US Classification:

326 93

Abstract:

A clock distribution network and mechanisms therein for an integrated circuit (IC) including an edge clock and distribution system for same. The invention includes a deskewed clock distribution network for circuits situated in columns wherein buffering is done in columns less than half of the IC length. The mechanism allows each of at least eight vertical column distribution lines to couple with any horizontal clock supply line of at least eight lines. The horizontal clock supply lines include local interconnect inputs. To increase clock source signals, special lines, Kx lines, are provided that are buffered and traverse directionally in 1/4 IC lengths from the top down, bottom up, and midsection both up and down. Kx lines can be sourced from carry signals, IOBs, interconnects, or from an edge clock and supply to clock lines, longlines, or interconnect lines. Kx lines allow vertical signal displacement, e. g.

US Patent:

55834523, Dec 10, 1996

Filed:

Oct 26, 1995

Appl. No.:

8/548926

Inventors:

Khue Duong - San Jose CA
Stephen M. Trimberger - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 190944

US Classification:

326 49

Abstract:

A configurable multi-directional buffer circuit for a programmable integrated circuit. The novel buffer circuit is a configurable multi-directional buffer circuit having one pair of inverters and having a first input/output line and a second input/output line and a third input line multiplexed with the first input/output line. The novel buffer circuit is configurable to allow a signal from the first input/output line to be driven over the second input/output line or configurable to allow a signal from the second input/output line to be driven over the first input/output line. The novel buffer circuit also allows a signal over the third input line to be driven over the second input/output line. In either case, only a single pair of inverter circuits are used. In an alternate embodiment, the novel buffer allows signal over a fourth input line to be driven over the first input/output line.

US Patent:

56752628, Oct 7, 1997

Filed:

Oct 26, 1995

Appl. No.:

8/548775

Inventors:

Khue Duong - San Jose CA
Stephen M. Trimberger - San Jose CA
Bernard J. New - Los Gatos CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41

Abstract:

A fast carry-out scheme in a field programmable logic array. The configurable logic blocks (CLBs) are arranged in columns. The carry-out signals are routed from the bottom CLB of a column to the top CLB of that column. The carry-out from the top-most CLB is then multiplexed onto a clock line that is normally used to conduct clocking signals to the CLBs. Instead of conducting clocking signals, the existing clock line is now used to route the carry-out signal onto a vertical longline spanning the entire height of the column. Eventually, the carry-out signal is routed from the longline to its destination CLB of the adjacent column via local interconnect resources.

US Patent:

56233876, Apr 22, 1997

Filed:

Jun 5, 1995

Appl. No.:

8/470555

Inventors:

Randy T. Ong - Cupertino CA
Samuel Broydo - Los Altos Hills CA
Khue Duong - San Jose CA

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H02H 904

US Classification:

361 56

Abstract:

An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp.

US Patent:

58805982, Mar 9, 1999

Filed:

Jan 10, 1997

Appl. No.:

8/781251

Inventors:

Khue Duong - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 738
H03K 19177

US Classification:

326 41

Abstract:

Signal routing resource tiles that can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a programmable logic device, e. g. , a field programmable gate array (FPGA). In one embodiment, vertical placement and horizontal placement routing resource tiles are provided. Routing resources tiles may be selectively added in areas of the programmable logic device determined to be prone to high signal congestion, e. g. , the central portions of the array, and along the array perimeter. The additional routing resource tiles simplify routing for complex logic functions and increase utilization of configurable logic blocks (CLBs) forming the array. The tiles can be positioned within the array in any position horizontally or vertically within the CLB array. Specifically, placement can be either in the core of the chip or along the periphery with each tile providing programmable connections to the existing routing resources (e. g. , input/output ports) within the CLBs.