Krste Asanovic

US Patent:

7287140, Oct 23, 2007

Filed:

Jul 27, 2004

Appl. No.:

10/899776

Inventors:

Krste Asanovic - Cambridge MA, US
Emmett J. Witchel - Austin TX, US

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

G06F 12/14

US Classification:

711163, 711208, 726 27

Abstract:

A fine-grained memory protection system and technique provide computer memory protection at least to a word granularity. A permissions table having permission values associated with a computer memory is arranged as protection domains. The permissions table can be cached in a protection lookaside buffer (PLD) and/or in sidecar registers. A software calls across protection domains (a cross-domain call) can be facilitated with a switch gate and a return gate. In some embodiments, a gate table is provided to store the switch gates and return gates, each having gate values. In some embodiments, a stack permission stable allows stack frames to be associated with the cross-domain call.

US Patent:

7398359, Jul 8, 2008

Filed:

Apr 30, 2004

Appl. No.:

10/836932

Inventors:

Steven C. Miller - Livermore CA, US
Martin M. Deneroff - Oakhurst NJ, US
Curt F. Schimmel - San Ramon CA, US
Larry Rudolph - Brookline MA, US
Charles E. Leiserson - Cambridge MA, US
Bradley C. Kuszmaul - Lexington MA, US
Krste Asanovic - Cambridge MA, US

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 12/00

US Classification:

711141, 711156, 717127, 717128

Abstract:

A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.

US Patent:

7925839, Apr 12, 2011

Filed:

Jul 7, 2008

Appl. No.:

12/168689

Inventors:

Steven C. Miller - Livermore CA, US
Martin M. Deneroff - Oakhurst NJ, US
Curt F. Schimmel - San Ramon CA, US
Larry Rudolph - Brookline MA, US
Charles E. Leiserson - Cambridge MA, US
Bradley C. Kuszmaul - Lexington MA, US
Krste Asanovic - Cambridge MA, US

Assignee:

Silicon Graphics International - Fremont CA

International Classification:

G06F 12/00

US Classification:

711141, 717127

Abstract:

A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.

US Patent:

8321634, Nov 27, 2012

Filed:

Apr 11, 2011

Appl. No.:

13/084280

Inventors:

Steven C. Miller - Livermore CA, US
Martin M. Deneroff - Oakhurst NJ, US
Curt F. Schimmel - San Ramon CA, US
Larry Rudolph - Brookline MA, US
Charles E. Leiserson - Cambridge MA, US
Bradley C. Kuszmaul - Lexington MA, US
Krste Asanovic - Cambridge MA, US

Assignee:

Silicon Graphics International Corp. - Fremont CA

International Classification:

G06F 12/00

US Classification:

711141, 711127

Abstract:

A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.

US Patent:

20130080709, Mar 28, 2013

Filed:

Nov 21, 2012

Appl. No.:

13/683367

Inventors:

Steven C. Miller - Livermore CA, US
Martin M. Deneroff - Oakhurst NJ, US
Curt F. Schimmel - San Ramon CA, US
Larry Rudolph - Brookline MA, US
Charles E. Leiserson - Cambridge MA, US
Bradley C. Kuszmaul - Lexington MA, US
Krste Asanovic - Cambridge MA, US

International Classification:

G06F 12/08

US Classification:

711143

Abstract:

A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line are not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.

US Patent:

58058753, Sep 8, 1998

Filed:

Sep 13, 1996

Appl. No.:

8/713748

Inventors:

Krste Asanovic - Berkeley CA

Assignee:

International Computer Science Institute - Berkeley CA

International Classification:

G06F 930

US Classification:

395563

Abstract:

A data processing system contains both a scalar processor and a vector processor. The vector processor contains a plurality of functional units, each of which contains a plurality of parallel pipelines. Each of the pipelines contains a plurality of arithmetic and logic units (ALUs) connected via a plurality of data paths, such that data can be communicated between the ALUs during the execution of a vector instruction by the vector functional unit containing the pipeline. The operation performed by each of the cascaded ALUs and the paths through which data is to be communicated between the ALUs during the execution of a vector instruction can be controlled by configuration values held in a scalar register named by the vector instruction. Through the use of this technique, multiple operations upon sets of vector data may be specified in a single short vector instruction, and further, the configuration of the pipelines can be determined dynamically in response to program input.

US Patent:

20220292183, Sep 15, 2022

Filed:

May 27, 2022

Appl. No.:

17/826622

Inventors:

- San Mateo CA, US
Krste Asanovic - Oakland CA, US
Yann Loisel - La Ciotat, FR
Cyril Bresch - Marseille, FR

Assignee:

SiFive, Inc. - San Mateo CA

International Classification:

G06F 21/52

Abstract:

Systems and methods are disclosed for secure control flow prediction. Some implementations may be used to eliminate or mitigate the Spectre-class of attacks in a processor. For example, an integrated circuit (e.g., a processor) for executing instructions may include a control flow predictor with entries that include branch target addresses associated with instructions. The branch target addresses may be predictions. A context tag associated with an entry may be compared to a context identifier associated with a currently executing process. Responsive to a mismatch between the context tag and the context identifier, the control flow predictor may provide an alternate value in place of a branch target address.

US Patent:

20220236993, Jul 28, 2022

Filed:

Apr 11, 2022

Appl. No.:

17/718258

Inventors:

- San Mateo CA, US
Krste Asanovic - Berkeley CA, US
Andrew Waterman - Berkeley CA, US

International Classification:

G06F 9/38
G06F 9/30
G06F 9/32

Abstract:

Systems and methods are disclosed for fetch stage handling of indirect jumps in a processor pipeline. For example, a method includes detecting a sequence of instructions fetched by a processor core, wherein the sequence of instructions includes a first instruction, with a result that depends on an immediate field of the first instruction and a program counter value, followed by a second instruction that is an indirect jump instruction; responsive to detection of the sequence of instructions, preventing an indirect jump target predictor circuit from generating a target address prediction for the second instruction; and, responsive to detection of the sequence of instructions, determining a target address for the second instruction before the first instruction is issued to an execution stage of a pipeline of the processor core.