Lansing D Pickup

US Patent:

7495492, Feb 24, 2009

Filed:

Sep 12, 2006

Appl. No.:

11/530981

Inventors:

Pascal A. Nsame - Colchester VT, US
Anthony J. Perri - Jericho VT, US
Lansing U. Pickup - Raleigh NC, US
Sebastian T. Ventrone - South Burlington VT, US
Matthew R. Walland - Chandler AZ, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 3/289

US Classification:

327202, 327203

Abstract:

The invention comprises a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.

US Patent:

7966589, Jun 21, 2011

Filed:

Apr 8, 2008

Appl. No.:

12/099423

Inventors:

Pascal A. Nsame - Colchester VT, US
Anthony J. Perri - Jericho VT, US
Lansing D. Pickup - Williston VT, US
Sebastian T. Ventrone - South Burlington VT, US
Matthew R. Welland - Tempe AZ, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716100, 716111, 716119, 716126, 716127, 716133, 327199, 327202, 327203, 327204, 365154

Abstract:

The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.

US Patent:

8381161, Feb 19, 2013

Filed:

Nov 4, 2011

Appl. No.:

13/289140

Inventors:

William R. Andersen - Milton VT, US
Oded Katz - Haifa, IL
Rina Kipnis - Karmiel, IL
Lansing D. Pickup - Raleigh NC, US
Christopher B. Reynolds - Milton VT, US
Joseph H. Underwood - Apalachin NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716119, 716 55, 716111, 716112, 716139

Abstract:

A computer-implemented method identifies at least one proprietary geometric figure from a plurality of geometric figures within a design data layout format file. The proprietary geometric figure in the design data layout format file may be replaced with a placeholder geometric figure. Cell names and connection names associated with the proprietary geometric figure are renamed from a netlist file that defines electrical connections between the geometric figures with obfuscating names. A modified design data layout format file may be generated that includes the placeholder geometric figure and a modified netlist file including the obfuscating names. The modified file enables IC designers to complete their design and checking activities, but inhibits reverse-engineering of the proprietary geometric & netlist data.

US Patent:

57743800, Jun 30, 1998

Filed:

Mar 8, 1996

Appl. No.:

8/613275

Inventors:

Lansing Dunn Pickup - Colchester VT
Paul Richard Schwartz - Williston VT
Todd William Westervelt - Colchester VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1520

US Classification:

364578

Abstract:

A Verilog simulation method significantly reduces scenario execution time of very large scale integrated (VLSI) logic models that contain high numbers of sequential devices. A computer implemented method saves the state of sequential devices into a file at a chosen point in a simulation scenario and then inputs this file to initialize another simulation scenario. The method has the ability to utilize the user defined primitive (UDP) model data for the sequential devices present in the technology library. However, using the standard data structure available in the programming language interface (PLI), it is not possible to uniquely identify individual UDPs. UDPs have the characteristic of having only one output each. Therefore, it is possible to uniquely identify each UDP by the net name which is connected to this output. An exception to this is the situation where two or more like-named UDP outputs are connected to the same net.

US Patent:

20190340323, Nov 7, 2019

Filed:

Jul 18, 2019

Appl. No.:

16/515177

Inventors:

- Armonk NY, US
John P. DUBUQUE - Jericho VT, US
Eric A. FOREMAN - Fairfax VT, US
Jeffrey G. HEMMETT - St. George VT, US
Lansing D. PICKUP - Raleigh NC, US
Natesan VENKATESWARAN - Hopewell Junction NY, US
Chandramouli VISWESWARIAH - Croton-on-Hudson NY, US
Vladimir ZOLOTOV - Putnam Valley NY, US

International Classification:

G06F 17/50

Abstract:

Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.

US Patent:

20150242554, Aug 27, 2015

Filed:

Feb 26, 2014

Appl. No.:

14/190646

Inventors:

- Armonk NY, US
John P. DUBUQUE - Jericho VT, US
Eric A. FOREMAN - Fairfax VT, US
Jeffrey G. HEMMETT - St George VT, US
Lansing D. PICKUP - Raleigh NC, US
Natesan VENKATESWARAN - Hopewell Junction NY, US
Chandramouli VISWESWARIAH - Croton-on-Hudson NY, US
Vladimir ZOLOTOV - Putnam Valley NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 17/50

Abstract:

Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.