Laurent Nathalia Isenegger

US Patent:

20230060826, Mar 2, 2023

Filed:

Sep 1, 2021

Appl. No.:

17/464516

Inventors:

- Boise ID, US
Jeffrey L. Scott - Apex NC, US
Laurent Isenegger - Morgan Hill CA, US
Robert M. Walker - Raleigh NC, US

International Classification:

G06F 3/06

Abstract:

A system includes a processing device that determines whether a memory bank is active and adds an activate command for a row of the memory bank accessed by an oldest command for the memory bank to a command scheduler in response to determining the memory bank is not active. The processing device determines whether the row of the memory bank has a corresponding row command in response to determining the memory bank is active. The processing device determines whether a close page mode is enabled or an open row timer has expired on the row and adds a precharge command to the command scheduler in response to determining the close page mode is enabled or the open row timer has expired. The processing device executes a command in the command scheduler based on a priority of commands included in the command scheduler.

US Patent:

20230060874, Mar 2, 2023

Filed:

Sep 1, 2021

Appl. No.:

17/463995

Inventors:

- Boise ID, US
Kirthi Ravindra Kulkarni - San Jose CA, US
Laurent Isenegger - Morgan Hill CA, US

International Classification:

G06F 13/16

Abstract:

A method includes determining a traffic pattern of access requests within a queue or a system, or both and dynamically adjusting, within a particular range, a queue depth of the queue based on the determined traffic pattern of access requests to balance bandwidth and latency associated with executing the access requests.

US Patent:

20230062167, Mar 2, 2023

Filed:

Aug 25, 2021

Appl. No.:

17/412037

Inventors:

- Boise ID, US
Laurent Isenegger - Morgan Hill CA, US
Kirthi Ravindra Kulkarni - San Jose CA, US

International Classification:

G11C 11/4076
G11C 11/4078
G11C 11/4093
G11C 11/4096

Abstract:

A method includes receiving a write request to a write queue of a host having the write queue and a read queue; initiating a write queue timer upon receiving the write request to the write queue of the host, wherein the write queue timer has a write queue timer expiry threshold value; and executing one or more write requests when the write queue timer reaches the write queue timer expiry threshold value.

US Patent:

20230065395, Mar 2, 2023

Filed:

Aug 30, 2021

Appl. No.:

17/461502

Inventors:

- Boise ID, US
Kirthi Ravindra Kulkarni - San Jose CA, US
Dhawal Bavishi - San Jose CA, US
Laurent Isenegger - Morgan Hill CA, US

International Classification:

G06F 3/06

Abstract:

A method includes enqueuing host commands of a first type and a second type in a command queue of a host memory controller and preventing a subsequent host command of the first type from being inserted into the command queue responsive to determining that a quantity of host commands of the first type and enqueued in the command queue having met a criterion.

US Patent:

20230067576, Mar 2, 2023

Filed:

Aug 30, 2021

Appl. No.:

17/461701

Inventors:

- Boise ID, US
Laurent Isenegger - Morgan Hill CA, US

International Classification:

G06F 3/06

Abstract:

A request can be provided, from a front-end of a memory sub-system, to a processing device of the memory sub-system and deleting the request from a buffer of the front-end of the memory sub-system. Responsive to deleting the request from the buffer, determining a first quantity of requests in the buffer and responsive to deleting the requests from the buffer, determining a second quantity of outstanding requests in the back-end of the memory sub-system. Responsive to deleting the request from the buffer and providing the request to the processing device, determining whether to provide a response to a host, wherein the response includes an indication of the quantity of requests in the buffer and of outstanding requests in a back-end of the memory sub-system, based on a comparison of the second quantity of outstanding requests to a threshold.