Lawrence D Curley

US Patent:

6469743, Oct 22, 2002

Filed:

Jun 9, 1999

Appl. No.:

09/328757

Inventors:

Dennis P. Cheney - Vestal NY
Lawrence D. Curley - Endwell NY
William R. Lee - Apex NC
Leland D. Richardson - Apex NC
Ronald S. Svec - Berkshire NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04N 544

US Classification:

348553, 348705, 345520, 345501, 326 37, 326 38

Abstract:

A programmable bi-directional external graphics/video (EGV) port for a video decode system chip having a video decoder and an internal digital display generator circuit is provided. The programmable EGV port employs a fixed number of signal input/output (I/O) pins on the video decode system chip while providing a plurality of connection configurations for an external graphics controller, an external digital display generator circuit and an external digital multi-standard decoder to the video decoder or the internal digital display generator circuit of the chip. The EGV port includes receiver/driver circuitry for accommodating in parallel a plurality of input/output signals, including pixel data signals and corresponding synchronization signals, as well as a programmable port controller adapted to be coupled between the receiver/driver circuitry and an internal bus of the video decode system allowing access to at least one of the video decoder and the internal digital display generator circuit. The programmable port controller is programmable to either receive data into the video decode system chip or to send data out from the video decode system chip.

US Patent:

6519283, Feb 11, 2003

Filed:

Jun 9, 1999

Appl. No.:

09/328756

Inventors:

Dennis P. Cheney - Vestal NY
Lawrence D. Curley - Endwell NY
William R. Lee - Apex NC
Leland D. Richardson - Apex NC
Ronald S. Svec - Berkshire NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04B 166

US Classification:

37524001, 348568, 725139

Abstract:

An integrated digital video system is configured to implement picture-in-picture merging of video signals from two or more video sources, as well as selective overlaying of on-screen display graphics onto the resultant merged signal. The picture-in-picture signal is produced for display by a television system otherwise lacking picture-in-picture capability. The digital video system can be implemented, for example, as an integrated decode system within a digital video set-top box or a digital video disc player. In one implementation, a decompressed digital video signal is downscaled and merged with an uncompressed video signal to produce the multi-screen display. The uncompressed video signal can comprise either analog or digital video. OSD graphics can be combined within the integrated system with the resultant multi-screen display or only with a received uncompressed analog video signal.

US Patent:

6714826, Mar 30, 2004

Filed:

Mar 13, 2000

Appl. No.:

09/524461

Inventors:

Lawrence D. Curley - Endwell NY
James F. Driftmyer - Endwell NY
Eric M. Foster - Owego NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1700

US Classification:

700 94, 725131

Abstract:

A processing facility is provided for simultaneously receiving multiple streams of digital audio data and based thereon concurrently outputting both an unmixed digital audio signal and a mixed digital audio signal. The processing facility can be implemented, for example, within an audio decoder of a set top box. The facility includes receiving a first stream of digital audio data and a second stream of digital audio data, and outputting the first stream of digital audio data as an unmixed digital audio signal. Simultaneous therewith, the first stream of digital audio data and the second stream of digital audio data are digitally mixed and outputted as a mixed digital audio signal. If necessary, the second stream of digital audio data is redigitized based on a sample frequency of the first stream of digital audio data, and either or both the first stream and second stream of digital audio data are decoded prior to mixing.

US Patent:

7979732, Jul 12, 2011

Filed:

Jul 3, 2007

Appl. No.:

11/772908

Inventors:

Lawrence D. Curley - Round Rock TX, US
John M. Isakson - Austin TX, US
Arjen Mets - Sleepy Hollow NY, US
Travis W. Pouarz - Austin TX, US
Thomas E. Rosser - Austin TX, US
Kristen M. Tucker - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/12
G06F 1/14

US Classification:

713600, 713400, 713401, 713500, 713501, 713502, 713503, 713601, 716113, 716114

Abstract:

A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.

US Patent:

7979838, Jul 12, 2011

Filed:

Feb 15, 2008

Appl. No.:

12/032517

Inventors:

Christopher J. Berry - Hudson NY, US
Jose Luis Pontes Correia Neves - Poughkeepsie NY, US
Lawrence David Curley - Round Rock TX, US
Patrick James Meaney - Poughkeepsie NY, US
Travis Wellington Pouarz - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716139, 716108

Abstract:

The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.

US Patent:

7987400, Jul 26, 2011

Filed:

Feb 22, 2008

Appl. No.:

12/035500

Inventors:

Christopher J. Berry - Hudson NY, US
Lawrence David Curley - Round Rock TX, US
Patrick James Meaney - Poughkeepsie NY, US
Diana Lynn Orf - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28
G06F 17/50

US Classification:

714726, 714729, 716122, 716125

Abstract:

A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned.

US Patent:

8364904, Jan 29, 2013

Filed:

Jun 21, 2010

Appl. No.:

12/819348

Inventors:

Michael A. Blake - Wappingers Falls NY, US
Lawrence D. Curley - Endwell NY, US
Garrett M. Drapala - Poughkeepsie NY, US
Edward J. Kaminski - Wynnewood PA, US
Craig R. Walters - Highland NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711141

Abstract:

Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.

US Patent:

8479070, Jul 2, 2013

Filed:

Jun 24, 2010

Appl. No.:

12/822287

Inventors:

Ulrich Baur - Boeblingen, DE
Lawrence D. Curley - Endwell NY, US
Ronald J. Frishmuth - Poughkeepsie NY, US
Ralf Ludewig - Schoenaich, DE
Ching L. Tong - Highland Mills NY, US
Tobias Webel - Schwaebisch-Gmuend, DE

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714734, 714733, 714 25, 714724, 324527, 3247503, 32475401, 32476201, 324719, 324724

Abstract:

An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.