Louise Y Yeung

US Patent:

6438613, Aug 20, 2002

Filed:

Jan 22, 1998

Appl. No.:

09/012025

Inventors:

Louise Y. Yeung - Redwood City CA
Rasoul M. Oskouy - Fremont CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 1300

US Classification:

709250, 709236, 709246, 709230

Abstract:

A network adapter for allowing packet data to be separated over multiple bus targets, without impact to input/output bus bandwidth or network performance, having: a bus interface circuit; a bus protocol circuit coupled to the bus interface circuit; a burst dispatcher circuit coupled to the bus protocol circuit; a network interface coupled to a read processing circuit and a write processing circuit, wherein the read processing circuit and the write processing circuit are coupled to the burst dispatcher; and, a synchronization and buffering circuit coupled to the bus protocol circuit, the burst dispatcher circuit, the read processing circuit and the write processing circuit. A method for transferring packet data between a first bus target, a second bus target, and the network adapter comprising the steps of creating a set of descriptor entries in the network adapter, wherein one descriptor entry is generated for each portion of each packet to be transmitted between either the first bus target or the second bus target, and the network adapter; and, transferring a portion of packet data from either the first bus target or the second bus target to the network adapter, wherein the bus target on which the portion of packet data is contained is described by one of the set of descriptor entries.

US Patent:

7203192, Apr 10, 2007

Filed:

Jun 4, 2002

Appl. No.:

10/163261

Inventors:

Sachin Desai - Santa Clara CA, US
Tim Millet - Mountain View CA, US
Zahid Hussain - San Jose CA, US
Paul Kim - Fremont CA, US
Louise Yeung - San Carlos CA, US
Ken Yeung - San Jose CA, US

Assignee:

Fortinet, Inc. - Sunnyvale CA

International Classification:

H04L 12/54
H04J 3/16
H04J 3/22

US Classification:

370389, 370428, 370467

Abstract:

Methods and Systems are provided for steering network packets and bridging media channels to a single processing resource. A mapping associates a processing resource with a network interface module (Netmod) or a number of line interface ports included within the Netmod. In one embodiment, the mapping is configurable within the processing resource and pushed to the Netmod. The Netmod uses the mapping to steer network packets to the processing resource when the packets conform to the mapping. Moreover, the mapping can be used to identify a specific process that is to be performed against the packets once the processing resource receives the steered packets from the Netmod.

US Patent:

8068503, Nov 29, 2011

Filed:

Mar 10, 2007

Appl. No.:

11/684614

Inventors:

Sachin Desai - Santa Clara CA, US
Tim Millet - Mountain View CA, US
Zahid Hussain - San Jose CA, US
Paul Kim - Fremont CA, US
Louise Yeung - San Jose CA, US
Ken Yeung - San Jose CA, US

Assignee:

Fortinet, Inc. - Sunnyvale CA

International Classification:

H04L 12/28

US Classification:

370400, 370389, 370392, 370401

Abstract:

Methods and systems are provided for steering network packets. According to one embodiment, a mapping associates a processing resource with a network interface module (netmod) and/or a number of line interface ports included within the netmod. In one embodiment, the mapping is configurable within the processing resource and pushed to the netmod. The netmod uses the mapping to steer network packets to the processing resource when the packets conform to the mapping. The mapping may be additionally used to identify a specific process that is to be performed against the packets once the processing resource receives the steered packets from the netmod.

US Patent:

8176304, May 8, 2012

Filed:

Oct 22, 2008

Appl. No.:

12/256250

Inventors:

Rahoul Puri - Los Altos CA, US
Arvind Srinivasan - San Jose CA, US
Louise Y. Yeung - Palo Alto CA, US
Marcelino M. Dignum - Menlo Park CA, US
John E. Watkins - Sunnyvale CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 9/00
G06F 15/177
G06F 1/24
G06F 3/00
G06F 13/00

US Classification:

713 1, 713 2, 713100, 710 1, 710100

Abstract:

An I/O device having function level reset functionality includes a host interface that may include a master reset unit, a plurality of client interfaces, each corresponding to one or more functions, and a plurality of hardware resources. Each hardware resource may be associated with a respective function. In response to receiving a reset request to reset a specific function, the master reset unit may provide to each client interface, a request signal corresponding to the reset request, and a signal identifying the specific function. Each client interface having an association with the specific function may initiate a reset operation of the associated hardware resources, and also provide a client reset done signal for the specific function to the master reset unit in response to completion of the reset operations of the hardware resources. The master reset unit provides a reset done signal for the specific function to the host interface.

US Patent:

8306040, Nov 6, 2012

Filed:

Jun 2, 2009

Appl. No.:

12/477124

Inventors:

Sachin Desai - Santa Clara CA, US
Tim Millet - Mountain View CA, US
Zahid Hussain - San Jose CA, US
Paul Kim - Fremont CA, US
Louise Yeung - San Jose CA, US
Ken Yeung - San Jose CA, US

Assignee:

Fortinet, Inc. - Sunnyvale CA

International Classification:

H04L 12/26

US Classification:

370400, 370389, 370392, 370401

Abstract:

Methods and systems are provided for steering network packets. According to one embodiment a method is provided for steering incoming network packets. Each network packet processing resource of a network routing/switching device is dynamically assigned to one or more network interfaces of the network routing/switching device. Each of the network packet processing resources includes one or more processing elements and a memory. Incoming network packets received by the network interfaces are steered to an appropriate network packet processing resource based on the dynamic assignment.

US Patent:

8638802, Jan 28, 2014

Filed:

Nov 29, 2011

Appl. No.:

13/305804

Inventors:

Sachin Desai - Santa Clara CA, US
Tim Millet - Mountain View CA, US
Zahid Hussain - San Jose CA, US
Paul Kim - Fremont CA, US
Louise Yeung - San Jose CA, US
Ken Yeung - San Jose CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04L 12/26

US Classification:

370400, 370389, 370392, 370401

Abstract:

Methods and systems are provided for steering network packets. According to one embodiment, a dynamically configurable steering table is stored within a memory of each network interface of a networking routing/switching device. The steering table represents a mapping that logically assigns each of the network interfaces to one of multiple packet processing resources of the network routing/switching device. The steering table has contained therein information indicative of a unique identifier/address of the assigned packet processing resource. Responsive to receiving a packet on a network interface, the network interface performs Layer 1 or Layer 2 steering of the received packet to the assigned packet processing resource by retrieving the information indicative of the unique identifier/address of the assigned packet processing resource from the steering table based on a channel identifier associated with the received packet and the received packet is processed by the assigned packet processing resource.

US Patent:

59096861, Jun 1, 1999

Filed:

Jun 30, 1997

Appl. No.:

8/885047

Inventors:

Shimon Muller - Sunnyvale CA
Ariel Hendel - Cupertino CA
Louise Yeung - San Carlos CA
Leo Hejza - Sunnyvale CA
Shree Murthy - Sunnyvale CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 1730

US Classification:

707104

Abstract:

A method and apparatus for providing hardware-assisted CPU access to a forwarding database is described. According to one aspect of the present invention, a switch fabric provides access to a forwarding database on behalf of a processor. The switch fabric includes a memory access interface configured to arbitrate access to a forwarding database memory. The switch fabric also includes a search engine coupled to the memory access interface and to multiple input ports. The search engine is configured to schedule and perform accesses to the forwarding database memory and to transfer forwarding decisions retrieved therefrom to the input ports. The switch fabric further includes command execution logic that is configured to interface with the processor for performing forwarding database accesses requested by the processor. According to another aspect of the invention one or more commands are provided to implement the following functions: (1) learning a supplied address; (2) reading associated data corresponding to a supplied search key; (3) aging forwarding database entries; (4) invalidating entries; (5) accessing mask data, such as mask data that may be stored in a mask per bit (MPB) content addressable memory (CAM), corresponding to a particular search key; (6) replacing forwarding database entries; and (7) accessing entries in the forwarding database.

US Patent:

56383673, Jun 10, 1997

Filed:

Jul 7, 1995

Appl. No.:

8/498620

Inventors:

Andre J. Gaytan - Union City CA
Louise Yeung - Redwood City CA

Assignee:

Sun Microsystems, Inc. - CA

International Classification:

H04J 316

US Classification:

370471

Abstract:

A scalable packing circuit used to byte pack data transferred from a first storage element to a second storage element. The packing circuitry comprises a word packing circuit which receives data packets of a first bit width and stores them as data packets of a second bit width equivalent to the bit width of the second storage element. Concurrently, the word packing circuit eliminates invalid words included within the data packets from the first storage element. The packing circuit also includes a byte packing circuit which removes invalid bytes within the data packets of the second bit width before transferring the data to the second storage element for contiguous storage.