Mangesh P Nijasure

US Patent:

20120017062, Jan 19, 2012

Filed:

Jul 19, 2011

Appl. No.:

13/186038

Inventors:

Vineet GOEL - Winter Park FL, US
Todd Martin - Orlando FL, US
Mangesh Nijasure - Orlando FL, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 15/76
G06F 9/06
G06F 12/02

US Classification:

711170, 712 30, 712E09003, 711E12002

Abstract:

Methods are disclosed for improving data processing performance in a processor using on-chip local memory in multiple processing units. According to an embodiment, a method of processing data elements in a processor using a plurality of processing units, includes: launching, in each of the processing units, a first wavefront having a first type of thread followed by a second wavefront having a second type of thread, where the first wavefront reads as input a portion of the data elements from an off-chip shared memory and generates a first output; writing the first output to an on-chip local memory of the respective processing unit; and writing to the on-chip local memory a second output generated by the second wavefront, where input to the second wavefront comprises a first plurality of data elements from the first output. Corresponding system and computer program product embodiments are also disclosed.

US Patent:

20130162651, Jun 27, 2013

Filed:

Dec 23, 2011

Appl. No.:

13/336635

Inventors:

Todd Martin - Orlando FL, US
Mangesh Nijasure - Orlando FL, US
Vineet Goel - Winter Park FL, US
Jason David Carroll - Oviedo FL, US

International Classification:

G06T 11/20

US Classification:

345441

Abstract:

Methods, systems, and computer readable media embodiments are disclosed for generating primitives in a grid. Embodiments include generating a set of vertices in a section of the grid, selecting one or more vertices in the set of vertices in an order based on a proximity of the vertices to a boundary edge of the grid, and generating primitives based on the order of the selected vertices.

US Patent:

20130169634, Jul 4, 2013

Filed:

Apr 18, 2012

Appl. No.:

13/449410

Inventors:

Vineet GOEL - Winter Park FL, US
Jason David Carroll - Oviedo FL, US
Mangesh Nijasure - Orlando FL, US
Todd Martin - Orlando FL, US

International Classification:

G06T 17/20

US Classification:

345423

Abstract:

Embodiments include an apparatus, a computer readable medium and a method for distributing tessellations within an accelerated processing device (APD) including at least two compute units. Embodiments include processing a plurality of patches in a first compute unit using a hull shader to generate hull shader output data. Once generated, hull shader output data is stored to an off-chip memory when tessellation factors associated with the shader program are greater than a configured threshold. Once stored in the off-chip memory, at least a portion of the hull shader output data is dynamically processed using a second compute unit.

US Patent:

20130169635, Jul 4, 2013

Filed:

May 22, 2012

Appl. No.:

13/477808

Inventors:

Jason CARROLL - Oviedo FL, US
Vineet GOEL - Winter Park FL, US
Mangesh NIJASURE - Orlando FL, US
Todd E. MARTIN - Orlando FL, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06T 11/20
G06T 17/20

US Classification:

345423, 345441

Abstract:

Disclosed herein is a vertex core. The vertex core includes a reset scanner configured to remove reset indices and partial primitives in an input stream and resolve draw calls into sub-draw calls at reset index boundaries; and provide the resolved sub-draw calls to a plurality of downstream vertex grouper tessellators.

US Patent:

20140078156, Mar 20, 2014

Filed:

Sep 14, 2012

Appl. No.:

13/616474

Inventors:

Jason Carroll - Oviedo FL, US
Vineet Goel - Winter Park FL, US
Mangesh Nijasure - Orlando FL, US
Todd E. Martin - Orlando FL, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06T 1/20

US Classification:

345505

Abstract:

A system, method and a computer program product are provided for distributing prim groups for parallel processing in a single clock cycle. A work distributor divides a draw call for primitive processing into a plurality of prim groups according to a prim group size. The work distributor then distributes the plurality of prim groups to a plurality of shader engines for parallel processing of the plurality of prim groups during a clock cycle. The size of a prim group and a number of prim groups are scaled to the plurality of shader engines.

US Patent:

20110057931, Mar 10, 2011

Filed:

Feb 18, 2010

Appl. No.:

12/708331

Inventors:

Vineet GOEL - Winter Park FL, US
Jason David CARROLL - Oviedo FL, US
Brian BUCHNER - Oviedo FL, US
Mangesh NIJASURE - Orlando FL, US

International Classification:

G06T 17/20

US Classification:

345423

Abstract:

Disclosed herein methods, apparatuses, and systems for performing graphics processing. In this regard, a processing unit includes a tessellation module and a connectivity module. The tessellation module is configured to sequentially tessellate portions of a geometric shape to provide a series of tessellation points for the geometric shape. The connectivity module is configured to connect one or more groups of the tessellation points into one or more primitives in an order in which the series of tessellation points is provided.

US Patent:

20210295585, Sep 23, 2021

Filed:

Mar 20, 2020

Appl. No.:

16/825600

Inventors:

- Santa Clara CA, US
Vishrut VAIBHAV - Orlando FL, US
Mangesh P. NIJASURE - Orlando FL, US
Todd MARTIN - Orlando FL, US

International Classification:

G06T 15/00

Abstract:

A graphics pipeline includes a tessellator stage having a sub-patch distributor and a plurality of tessellators. The sub-patch distributor divides an input patch into a plurality of sub-primitive groups, with the primitive group limit governing the maximum permissible size for a given group of sub-primitives to be assigned to a tessellator. The sub-patch distributor recursively identifies a plurality of regions of the input patch, with the size and number of primitives of each region based on the specified primitive group limit. The sub-patch distributor assigns different regions to different sub-patch groups and distributes the sub-patch groups among the plurality of tessellators.

US Patent:

20210090205, Mar 25, 2021

Filed:

Sep 24, 2019

Appl. No.:

16/580654

Inventors:

- Santa Clara CA, US
Alexander Fuad ASHKAR - Orlando FL, US
Randy RAMSEY - Orlando FL, US
Mangesh P. NIJASURE - Orlando FL, US
Brian EMBERLING - Santa Clara CA, US

International Classification:

G06T 1/20
G06T 15/80
G06F 9/38

Abstract:

The address of the draw or dispatch packet responsible for creating an exception is tied to a shader/wavefront back to the draw command from which it originated. In various embodiments, a method of operating a graphics pipeline and exception handling includes receiving, at a command processor of a graphics processing unit (GPU), an exception signal indicating an occurrence of a pipeline exception at a shader stage of a graphics pipeline. The shader stage generates an exception signal in response to a pipeline exception and transmits the exception signal to the command processor. The command processor determines, based on the exception signal, an address of a command packet responsible for the occurrence of the pipeline exception.