Mark L Neidengard

US Patent:

7405631, Jul 29, 2008

Filed:

Jun 30, 2004

Appl. No.:

10/880693

Inventors:

Mark L. Neidengard - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 3/03

US Classification:

331 57, 327114

Abstract:

An oscillator includes a first circuit that asynchronously generates an oscillating signal in response to a second circuit of the oscillator acknowledging each cycle of the oscillating signal.

US Patent:

7667507, Feb 23, 2010

Filed:

Jun 26, 2008

Appl. No.:

12/146663

Inventors:

Mark L. Neidengard - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03L 7/06

US Classification:

327155, 327166, 327170

Abstract:

According to some embodiments, a method and system are provided to receive a clock input at a first clock adjustment tuner, receive the clock input at a second clock adjustment tuner, output a tuned inverted rising clock signal via the first clock adjustment tuner, output a tuned inverted falling clock signal via the second clock adjustment tuner, receive the inverted rising clock signal and the inverted falling clock signal at a clock synchronizer, output a synchronized tuned clock signal via the clock synchronizer, receive the synchronized tuned clock signal at a third clock adjustment tuner, and output a tuned clock signal. The first clock adjustment tuner and the second clock adjustment tuner provide coarser adjustments than the third clock adjustment tuner.

US Patent:

7679404, Mar 16, 2010

Filed:

Jun 23, 2006

Appl. No.:

11/474025

Inventors:

Mark L. Neidengard - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 5/19

US Classification:

327 18, 327 20

Abstract:

A method to detect a missing a clock pulse is provided. The method begins by providing a clock signal and a delayed clock signal. The delayed clock signal is then sampled to generate a sample of the delayed clock signal. A missing clock pulse may be detected if the sample of the delayed clock signal does not equal an expected value of the delayed clock signal.

US Patent:

20050195000, Sep 8, 2005

Filed:

Mar 5, 2004

Appl. No.:

10/794497

Inventors:

Rachael Parker - Forest Grove OR, US
Mark Neidengard - Hillsboro OR, US
Patrick Ott - Hillsboro OR, US
Gregory Taylor - Portland OR, US

International Classification:

H03L007/00

US Classification:

327143000

Abstract:

Embodiments of the present invention include a circuit, a method, and a system for power-on detect circuitry for use with multiple voltage domains.

US Patent:

20080258782, Oct 23, 2008

Filed:

Jun 19, 2008

Appl. No.:

12/214449

Inventors:

Mark L. Neidengard - Hillsboro OR, US

International Classification:

H03B 19/00

US Classification:

327117

Abstract:

An oscillator includes a first circuit that asynchronously generates an oscillating signal in response to a second circuit of the oscillator acknowledging each cycle of the oscillating signal.

US Patent:

20130086410, Apr 4, 2013

Filed:

Oct 1, 2011

Appl. No.:

13/251220

Inventors:

Nasser A. Kurd - Portland OR, US
Robert J. Greiner - Beaverton OR, US
Mark L. Neidengard - Beaverton OR, US
Vaughn J. Grossnickle - Beaverton OR, US

International Classification:

G06F 1/12
H03L 7/08

US Classification:

713501, 327157

Abstract:

Multi-tier methods and systems to synthesize a reference frequency, and control one or more tiers in view of multiple prioritized criteria. A first tier of a frequency synthesizer may include a first phase locked loop (PLL), which may include an inductive-capacitive voltage-controlled oscillator (LC VCO). One or more subsequent tiers may each include a second PLL, which may include a self-biased (SB) VCO PLL or a digitally-controlled oscillator (DCO) PPL. A subsequent tier may be controllable with respect to multiple parameters. Parameters may be evaluated and selected based on multiple criteria, which may be prioritized. Parameters may be selected, for example, to minimize a frequency error equal relative to a permissible deviation from a desired frequency as a first priority, reduce jitter as a second priority, and minimize a frequency error relative to the desired frequency as a third priority.

US Patent:

20210083678, Mar 18, 2021

Filed:

Sep 22, 2020

Appl. No.:

17/028923

Inventors:

- Santa Clara CA, US
Qi Wang - Portland OR, US
Mark L. Neidengard - Beaverton OR, US
Vaughn J. Grossnickle - Beaverton OR, US
Nasser A. Kurd - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03L 7/08
H03L 7/099
H03L 1/00
H03K 3/03

Abstract:

An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

US Patent:

20210049307, Feb 18, 2021

Filed:

Nov 2, 2020

Appl. No.:

17/087414

Inventors:

- Santa Clara CA, US
Praveen Mosalikanti - Portland OR, US
Thripthi Hegde - Beaverton OR, US
Mark Neidengard - Beaverton OR, US
Vaughn Grossnickle - Beaverton OR, US
Qi S. Wang - Portland OR, US
Kandadai Ramesh - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 21/70
H03K 5/24
H03K 21/08
G06F 1/28
G06F 1/06

Abstract:

An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.