Martin E Karlsson

US Patent:

7979640, Jul 12, 2011

Filed:

Jul 28, 2008

Appl. No.:

12/181266

Inventors:

Shailender Chaudhry - San Francisco CA, US
Robert E. Cypher - Saratoga CA, US
Martin Karlsson - San Francisco CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G06F 12/08

US Classification:

711128, 711165, 711E12018, 711E12061

Abstract:

Embodiments of the present invention provide a system that handles way mispredictions in a multi-way cache. The system starts by receiving requests to access cache lines in the multi-way cache. For each request, the system makes a prediction of a way in which the cache line resides based on a corresponding entry in the way prediction table. The system then checks for the presence of the cache line in the predicted way. Upon determining that the cache line is not present in the predicted way, but is present in a different way, and hence the way was mispredicted, the system increments a corresponding record in a conflict detection table. Upon detecting that a record in the conflict detection table indicates that a number of mispredictions equals a predetermined value, the system copies the corresponding cache line from the way where the cache line actually resides into the predicted way.

US Patent:

8041900, Oct 18, 2011

Filed:

Jan 15, 2008

Appl. No.:

12/014217

Inventors:

Paul Caprioli - Santa Clara CA, US
Martin Karlsson - San Francisco CA, US
Sherman H. Yip - San Francisco CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G06F 12/08

US Classification:

711145, 711E12041

Abstract:

Embodiments of the present invention provide a system that executes transactions on a processor that supports transactional memory. The system starts by executing the transaction on the processor. During execution of the transactions, the system places stores in a store buffer. In addition, the system sets a stores_encountered indicator when a first store is placed in the store buffer during the transaction. Upon completing the transaction, the system determines if the stores_encountered indicator is set. If so, the system signals a cache to commit the stores placed in the store buffer during the transaction to the cache and then resumes execution of program code following the transaction when the stores have been committed. Otherwise, the system resumes execution of program code following the transaction without signaling the cache.

US Patent:

8151084, Apr 3, 2012

Filed:

Jan 23, 2008

Appl. No.:

12/018407

Inventors:

Paul Caprioli - Santa Clara CA, US
Martin Karlsson - San Francisco CA, US
Shailender Chaudhry - San Francisco CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G06F 12/10

US Classification:

711205, 711118, 711122, 711137, 711221

Abstract:

Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.

US Patent:

8225139, Jul 17, 2012

Filed:

Jun 29, 2009

Appl. No.:

12/493447

Inventors:

Daniel S. Nussbaum - Cambridge MA, US
David Dice - Foxboro MA, US
Martin Karlsson - San Francisco CA, US
Mark S. Moir - Hampton NH, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G06F 9/00

US Classification:

714 16, 714 15

Abstract:

One embodiment provides a system that facilitates the execution of a transaction for a program in a hardware-supported transactional memory system. During operation, the system records a misspeculation indicator of the transaction during execution of the transaction using hardware transactional memory mechanisms. Next, the system detects a transaction failure associated with the transaction. Finally, the system provides the recorded misspeculation indicator to the program to facilitate a response to the transaction failure by the program.

US Patent:

8281185, Oct 2, 2012

Filed:

Jun 30, 2009

Appl. No.:

12/494934

Inventors:

Daniel S. Nussbaum - Cambridge MA, US
David Dice - Foxboro MA, US
Martin Karlsson - San Francisco CA, US
Mark S. Moir - Hampton NH, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G06F 11/00

US Classification:

714 15, 714 16, 707703

Abstract:

One embodiment provides a system that facilitates the execution of a transaction for a program in a hardware-supported transactional memory system. During operation, the system records a failure state of the transaction during execution of the transaction using hardware transactional memory mechanisms. Next, the system detects a transaction failure associated with the transaction. Finally, the system provides an advice state associated with the recorded failure state to the program to facilitate a response to the transaction failure by the program.

US Patent:

8285926, Oct 9, 2012

Filed:

May 3, 2010

Appl. No.:

12/772809

Inventors:

Martin R. Karlsson - San Francisco CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G06F 13/00
G06F 13/28

US Classification:

711113, 711E12024

Abstract:

The disclosed embodiments provide a system that filters duplicate requests from an L1 cache for a cache line. During operation, the system receives at an L2 cache a first request and a second request for the same cache line, and stores identifying information for these requests. The system then performs a cache array look-up for the first request that, in the process of creating a load fill packet for the first request, loads the cache line into a fill buffer. After sending the load fill packet for the first request to the L1 cache, the system uses the cache line data still stored in the fill buffer and stored identifying information for the second fill request to send a subsequent load fill packet for the second request to the L1 cache without performing an additional cache array look-up.

US Patent:

8327188, Dec 4, 2012

Filed:

Nov 13, 2009

Appl. No.:

12/618282

Inventors:

Martin R. Karlsson - San Francisco CA, US
Sherman H. Yip - San Francisco CA, US
Shailender Chaudhry - San Francisco CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G06F 11/00

US Classification:

714 15, 714 25

Abstract:

The described embodiments provide a processor (e. g. , processor ) for executing instructions. During execution, the processor starts by transactionally executing instructions from a protected section of program code. The processor then encounters a transactional failure condition while transactionally executing the instructions from the protected section of program code. In response to encountering the transactional failure condition, the processor enters a transactional-scout mode and speculatively executes subsequent instructions in the transactional-scout mode.

US Patent:

8341357, Dec 25, 2012

Filed:

Mar 16, 2010

Appl. No.:

12/724639

Inventors:

Martin R. Karlsson - San Francisco CA, US
Shailender Chaudhry - San Francisco CA, US
Robert E. Cypher - Saratoga CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G06F 12/08

US Classification:

711137, 711119, 711125, 711E12002, 711E12016, 711E12017, 711E12023, 712207

Abstract:

One embodiment provides a system that pre-fetches into a sibling cache. During operation, a first thread executes in a first processor core associated with a first cache, while a second thread associated with the first thread simultaneously executes in a second processor core associated with a second cache. During execution, the second thread encounters an instruction that triggers a request to a lower-level cache which is shared by the first cache and the second cache. The system responds to this request by directing a load fill which returns from the lower-level cache in response to the request to the first cache, thereby reducing cache misses for the first thread.