Matthias K Ilg

US Patent:

6376348, Apr 23, 2002

Filed:

Sep 30, 1997

Appl. No.:

08/940235

Inventors:

Martin Schrems - Langebrueck, DE
Matthias Ilg - Richmond VA

Assignee:

Siemens Aktiengesellschaft - Munich

International Classification:

H01L 213205

US Classification:

438592, 438594, 438491, 438244, 438542

Abstract:

Formation of a gate having a polysilicon and silicide layer thereover with reduced resistance and reduced thickness is provided. The polysilicon layer is annealed to diffuse the dopants out from the surface to reduce the dopant concentration to below the level which causes metal rich interface. Thus, a metal silicide layer can be deposited without an intrinsic poly cap layer or requiring the poly to having a decreased dopant concentration. As such, a thinner gate stack having lower sheet resistance and improved reliability is achieved.

US Patent:

6492282, Dec 10, 2002

Filed:

Apr 30, 1997

Appl. No.:

08/846925

Inventors:

Dirk Tobben - Fishkill NY
Peter Weigand - Croton on Hudson NY
Matthias Ilg - Fishkill NY

Assignee:

Siemens Aktiengesellschaft - Munich

International Classification:

H01L 21316

US Classification:

438760, 438780, 438795, 438564

Abstract:

A method of filling gaps between adjacent gate electrodes of a semiconductor structure. A self-planarizing material is deposited over the structure. A first portion of such material flow between the gate electrode to fill the gaps and a second portion of such material becomes deposited over tops of the gate electrodes and over the gaps to form a layer with a substantially planar surface. A phosphorous dopant is formed in the second portion of the self-planarizing material. Thus, relatively small gaps may be filled effectively with a layer having a very planar surface for subsequent photolithography. The phosphorous dopant provides gettering to remove adverse effects of alkali contaminant ions which may enter the gap filling material. The dielectric constant of the material filing the gaps, i. e. , the first portion of the gap filling material, being substantially free of such contaminants, has a relatively low dielectric constant thereby reducing electrical coupling between adjacent electrodes.

US Patent:

6492688, Dec 10, 2002

Filed:

Mar 2, 1999

Appl. No.:

09/260937

Inventors:

Matthias Ilg - Richmond VA

Assignee:

Siemens Aktiengesellschaft - Munich

International Classification:

H01L 2976

US Classification:

257369, 257407, 257412, 257392

Abstract:

A method for forming a CMOS device. The method includes forming a gate oxide over a surface of a semiconductor substrate. A first doped layer is formed over the gate oxide. The first doped layer is lithographically patterned comprising selectively removing a portion of such first doped layer to expose a first portion of the gate oxide with the first doped layer remaining disposed over a second laterally positioned portion of the gate oxide. A second doped is deposited over the patterned first doped layer, such second doped layer having a dopant different from, for example a conductivity type opposite to, the dopant of the first doped layer. A portion of the second doped layer is deposited over the exposed first portion of the gate oxide and over the first doped layer to provide a pair of vertically positioned regions. A lower region comprises a portion of the first doped layer and an upper region comprising a portion of the second doped layer. The second doped layer is lithographically patterned to form a pair of laterally spaced gate electrodes for the transistors, one of such gates comprising the patterned first doped layer and the other one of the gates comprising the patterned pair of vertically positioned regions.

US Patent:

61976660, Mar 6, 2001

Filed:

Sep 3, 1999

Appl. No.:

9/390496

Inventors:

Herbert Schafer - Hohenkirchen-Sieg Brunn, DE
Martin Franosch - Munchen, DE
Reinhard Stengl - Stadtbergen, DE
Hans Reisinger - Grunwald, DE
Matthias Ilg - Richmond VA

Assignee:

Siemens Aktiengesellschaft - Munich

International Classification:

H01L 2120

US Classification:

438509

Abstract:

A method for the fabrication of a doped silicon layer, includes carrying out deposition by using a process gas containing SiH. sub. 4, Si. sub. 2 H. sub. 6 and a doping gas. The doped silicon layer which is thus produced can be used both as a gate electrode of an MOS transistor and as a conductive connection. At a thickness between 50 and 200 nm it has a resistivity less than or equal to 0. 5 m. OMEGA. cm.

US Patent:

57539480, May 19, 1998

Filed:

Nov 19, 1996

Appl. No.:

8/752137

Inventors:

Son Van Nguyen - San Jose CA
Matthias Ilg - Fishkill NY
Kevin J. Uram - Union City CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2972

US Classification:

257307

Abstract:

Capacitor storage charge can be increased by increasing storage node area. A high aspect surface ratio stack capacitor is produced without increasing overall cell dimensions. The node is formed with layers of low doped and high doped concentration borophosphosilicate glass which is deposited by a single process step with precise nanometer dimensions, are selectively etched so that either doped or undoped layers will have a higher etch rate. This etching creates finger-like projections in the node, which provide for greater surface area using a very simplified process requiring fewer processing steps.

US Patent:

58077928, Sep 15, 1998

Filed:

Dec 18, 1996

Appl. No.:

8/768826

Inventors:

Matthias Ilg - Fishkill NY
Markus Kirchhoff - Wappingers Falls NY
Christoph Werner - Moosach, DE

Assignee:

Siemens Aktiengesellschaft - Munich

International Classification:

H01L 21316

US Classification:

438758

Abstract:

A method and apparatus for forming a multi-constituent device layer on a wafer surface are disclosed. The multi-constituent device layer is formed by flowing a first chemistry comprising a first constituent and a second chemistry comprising a second constituent via a segmented delivery system into a reaction chamber. The reaction chamber comprises a susceptor for supporting and rotating the wafers. The segmented delivery system comprises alternating first and second segments into which the first and second chemistries, respectively, are flowed. The first segments comprise an area that is greater than an area of the second segments by an amount sufficient to effectively reduce the diffusion path of the first constituent. Reducing the diffusion path of the first constituent results in a more uniform distribution of the first constituent within the device layer.

US Patent:

61909556, Feb 20, 2001

Filed:

Jan 27, 1998

Appl. No.:

9/014433

Inventors:

Matthias Ilg - Richmond VA
Richard L. Kleinhenz - Wappingers Falls NY
Soichi Nadahara - Kanagawa, JP
Ronald W. Nunes - Hopewell Junction NY
Klaus Penner - Attendorf-Okrilla, DE
Klaus Roithner - Assling, DE
Radhika Srinivasan - Mahwah NJ
Shigeki Sugimoto - Kanawawa, JP

Assignee:

International Business Machines Corporation - Armonk NY
Infineon Technologies North America Corp. - San Jose CA
Kabushiki Kaisha Toshiba - Kawasaki

International Classification:

H01L 218244

US Classification:

438238

Abstract:

Improved trench forming methods for semiconductor substrates using BSG avoid the problems associated with conventional TEOS hard mask techniques. The methods comprise: (a) providing a semiconductor substrate, (b) applying a conformal layer of borosilicate glass (BSG) on the substrate; (c) forming a patterned photoresist layer over the BSG layer whereby a portion of a layer underlying the photoresist layer is exposed, (d) anisotropically etching through the exposed portion of the underlying layer, through any other layers lying between the photoresist layer and the semiconductor substrate, and into the semiconductor substrate, thereby forming a trench in the semiconductor substrate. Preferably, one or more dielectric layers are present on the substrate surface prior to application of the BSG layer. One or more chemical barrier and/or organic antireflective coating layers may be applied over the BSG layer between the BSG layer and the photoresist layer.

US Patent:

60484756, Apr 11, 2000

Filed:

Sep 28, 1999

Appl. No.:

9/407384

Inventors:

Markus M. Kirchhoff - Ottendorf-Obrilla, DE
Matthias Ilg - Richmond VA

Assignee:

Siemens Aktiengesellschaft - Munich

International Classification:

C03C 1700
H01L 21302

US Classification:

252950

Abstract:

Improved gap fill of narrow spaces is achieved by using a doped silicate glass having a dopant concentration in a bottom portion thereof which is greater than an amount which causes surface crystal growth and in an upper portion thereof having a lower dopant concentration such that the overall dopant concentration of the doped silicate glass is below that which causes surface crystal growth.