Melaku L Teshome

US Patent:

20220180468, Jun 9, 2022

Filed:

Feb 17, 2022

Appl. No.:

17/674781

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Altug Koker - El Dorado Hills CA, US
Josh Mastronarde - Sacramento CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

US Patent:

20210256654, Aug 19, 2021

Filed:

Jan 29, 2021

Appl. No.:

17/161941

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Josh Mastronarde - Sacramento CA, US
Naveen Matam - Rancho Cordova CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

US Patent:

20210133913, May 6, 2021

Filed:

Oct 13, 2020

Appl. No.:

17/069188

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Altug Koker - El Dorado Hills CA, US
Josh Mastronarde - Sacramento CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

US Patent:

20200294180, Sep 17, 2020

Filed:

Mar 15, 2019

Appl. No.:

16/355303

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Josh Mastronarde - Sacramento CA, US
Naveen Matam - Rancho Cordova CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

US Patent:

20200294181, Sep 17, 2020

Filed:

Mar 15, 2019

Appl. No.:

16/355377

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Altug Koker - El Dorado Hills CA, US
Josh Mastronarde - Sacramento CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

US Patent:

20190095223, Mar 28, 2019

Filed:

Sep 26, 2017

Appl. No.:

15/716239

Inventors:

- Santa Clara CA, US
Josh B. Mastronarde - Sacramento CA, US
Melaku Teshome - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/44
G06F 1/32
G06F 13/42

Abstract:

Embodiments are generally directed to automatic waking of power domains for graphics configuration requests. An embodiment of an apparatus an interface to receive a graphics configuration request, wherein the graphics configuration request is directed to a target graphics register in a graphics domain; registers for storage of data, the registers including one or more configuration registers that are accessible for storage of the graphics configuration request; automatic power domain determination logic to determine a power domain for the target graphics register based on shared information accessed by the automatic power domain determination logic; and wake indication logic to determine whether the power domain for the target graphics register is in a reduced power state and, upon making a reduced power state determination, to generate a wake indication for the power domain.