Michael P Beakes

US Patent:

8381156, Feb 19, 2013

Filed:

Aug 25, 2011

Appl. No.:

13/217381

Inventors:

Michael P. Beakes - Yorktown Heights NY, US
Shih-Hsien Lo - Mount Kisco NY, US
Michael R. Scheuermann - Katonah NY, US
Matthew R. Wordeman - Kula HI, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716110

Abstract:

There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack.

US Patent:

8627240, Jan 7, 2014

Filed:

Jun 28, 2012

Appl. No.:

13/536163

Inventors:

Emrah Acar - Montvale NJ, US
Michael P. Beakes - Yorktown Heights NY, US
William M. Green - Astoria NY, US
Jonathan E. Proesel - Yorktown Heights NY, US
Alexander V. Rylyakov - Mount Kisco NY, US
Yurii A. Vlasov - Katonah NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 52, 716 30, 716 51, 716 53, 716 55, 716139, 385 14, 385 15

Abstract:

Methods for integrated electronic and photonic design include laying out electronic and photonic design components in a design environment; adjusting photonic components according to photonic design requirements using a processor; checking design rules for electronic and photonic components according to manufacturing requirements; and adjusting component positioning and size to reconcile conflicts between electronic and photonic components.

US Patent:

20140007032, Jan 2, 2014

Filed:

Jul 9, 2012

Appl. No.:

13/544134

Inventors:

Emrah Acar - Montvale NJ, US
Michael P. Beakes - Yorktown Heights NY, US
William M. Green - Astoria NY, US
Jonathan E. Proesel - Yorktown Heights NY, US
Alexander V. Rylyakov - Mount Kisco NY, US
Yurii A. Vlasov - Katonah NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G06F 17/50

US Classification:

716112

Abstract:

Systems for integrated electronic and photonic design include a graphical user interface (GUI) configured to lay out electronic and photonic design components in a design environment; a design rule checking (DRC) module configured to check design rules for electronic and photonic components according to manufacturing requirements; and a processor configured to adjust photonic components according to photonic design requirements and to reconcile conflicts between electronic and photonic components.

US Patent:

57480125, May 5, 1998

Filed:

Jan 5, 1996

Appl. No.:

8/583300

Inventors:

Michael Patrick Beakes - Yorktown Heights NY
Barbara Alane Chappell - Portland OR
Terry Ivan Chappell - Portland OR
Bruce Martin Fleischer - Mt. Kisco NY
Rudolf Adriaan Haring - Cortlandt Manor NY
Talal Kamel Jaber - Autin TX
Edward Seewann - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19003

US Classification:

326 93

Abstract:

A pulsed logic circuit test methodology and circuitry therefor are disclosed. The methodology and circuitry allow the inhibiting of reset pulses, the ability to force resets and the ability to test the circuit in a pseudo-static mode of operation.

US Patent:

61311820, Oct 10, 2000

Filed:

May 2, 1997

Appl. No.:

8/850037

Inventors:

Michael Patrick Beakes - Yorktown Heights NY
Barbara Alana Chappell - Portland OR
Terry Ivan Chappell - Portland OR
Gary S. Ditlow - Garrison NY
Barry Lee Dorfman - Austin TX
Bruce Martin Fleischer - Mount Kisco NY
Vinod Narayanan - Fishkill NY
Robert Alan Philhower - Carmel NY
George Anthony Sai Halasz - Mount Kisco NY
Ghavam Ghavami Shahidi - Emsford NY
David James Widiger - Pflugerville TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 8

Abstract:

A computer-based method automatically synthesizes, optimizes and compiles high performance control logic using SRCMOS LOGIC ARRAY MACROS, abbreviated as SLAMs. The method includes a series of steps that transform a high level design description into a set of SLAMs, and includes the steps of partitioning the logic description of a unit into blocks that are suitable for mapping to a target SLAM structure; mapping each logic partition to the target SLAM structure; creating a configuration and relative layout for the internal structure for each SLAM; creating an external description for each SLAM, each description being of sufficient detail to carry out physical design and integration of the unit which contains the SLAM; assembling the partitions implemented as SLAMs with other macros in the unit; resolving interface conflicts between the different macros by selecting appropriate signal interfaces for various SLAMs; repeatedly changing the external specifications of the various SLAMs; analyzing the performance of the unit; automatically compiling the schematic and layout of each SLAM within the unit based on the configuration and relative layout; and assembling the macros and analyzing the design for design rule violations.

US Patent:

56338201, May 27, 1997

Filed:

Jun 5, 1995

Appl. No.:

8/463146

Inventors:

Michael P. Beakes - Yorktown Heights NY
Barbara A. Chappell - Portland OR
Terry I. Chappell - Portland OR
Bruce M. Fleischer - Mount Kisco NY
Thao N. Nguyen - Katonah NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 750

US Classification:

364787

Abstract:

A parallel self-resetting parallel binary adder provides high speed addition and subtraction. The adder combines the advantages of a fully custom design methodology with the higher performance potential of self-resetting complementary metal oxide semiconductor (CMOS) circuits. The adder logic architecture is carry look-ahead with two bit groups and requires six rows of merge logic to calculate the carry out of the Most Significant Bit (MSB). Loading on the critical path of the adder is reduced by moving as many merge blocks as possible to later rows. This allows the fan-out per stage in the critical path to be reduced from around three to two or less. The adder utilizes a bubble pipelined circuit architecture. For the adder, a bubble pipe segment consists of a row of self-resetting circuit blocks. A fast cycle time and minimum delay for each block is achieved by using fast forward amplification of the leading edge of the pulsed input signals followed by quick self-resetting of all nodes back to their standby state.

US Patent:

60054166, Dec 21, 1999

Filed:

May 2, 1997

Appl. No.:

8/850190

Inventors:

Michael Patrick Beakes - Yorktown Heights NY
Barbara Alana Chappell - Portland OR
Terry Ivan Chappell - Portland OR
Gary S. Ditlow - Garrison NY
Barry Lee Dorfman - Austin TX
Bruce Martin Fleischer - Mount Kisco NY
Vinod Narayanan - Fishkill NY
David James Widiger - Pflugerville TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19096

US Classification:

326 96

Abstract:

A logic circuit family implements self-resetting CMOS logic array macros (SLAMs) which include a plurality of inputs to which a plurality of data input signals can be applied; a plurality of input buffers coupled to receive the input signals from the inputs; a NOR circuit coupled to receive the outputs of the input buffers and a pulsed logic timing signal synchronized within a predefined window with the arrival of the data input signals; an output buffer coupled to receive the output of the NOR circuit; and an output at which a data output signal is produced, with the output signal being a logical NOR of the data input signals; and with each of the NOR circuit, the plurality of input buffers, and the output buffer optionally having a separate reset input to reset it to a standby state. The SLAMs address the very high pressure on the performance of both control logic and control logic design systems. The distinguishing features of SLAMs are uniquely combined to allow the automated design, from a logic description and interface specifications, of a complete macro satisfying predetermined design guidelines.