Michael A Grosner

age ~57

from San Diego, CA

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Also known as:

Michael Andrew Grosner
Michael A Grosher
Michaela A Grosner
Mike A Grosner

Phone and address:: 7010 Astoria St, San Diego, CA 92111
8585651098

Connected to:

Michael Grosner Phones & Addresses

7010 Astoria St, San Diego, CA 92111 • 8585651098
4287 Corte De Sausalito, San Diego, CA 92130 • 8582599954
9816 Reagan Rd, San Diego, CA 92126 • 8585866674
1312 Pinnacle Peak Dr, Chula Vista, CA 91915
Saint Petersburg, FL
Clearwater, FL

Work

Company:

Appliedmicro
Feb 2008
Position:

Senior staff design engineer at applied micro

Education

Degree:

Bachelors, Bachelor of Science
School / High School:

University of Connecticut
1990 to 1990
Specialities:

Electronics Engineering

Skills

Asic • Verilog • Systemverilog • Rtl Design • Fpga • Soc • High Speed Digital Design • Debugging • Ic • Digital Ic Design • Functional Verification • Open Verification Methodology • Rtl Coding • Rtl Verification • Timing Closure • Static Timing Analysis • Processors

Industries

Semiconductors

Name / Title

Company / Classification

Phones & Addresses

Michael Andrew Grosner
President

AIDAN VENTURES, INC
Business Services

4603 Torrey Cir #V-106, San Diego, CA 92130
4287 Corte De Sausalito, San Diego, CA 92130

Resumes

Senior Staff Design Engineer At Applied Micro

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Location:

San Diego, CA

Industry:

Semiconductors

Work:

Appliedmicro
Senior Staff Design Engineer at Applied Micro
Idt - Integrated Device Technology, Inc. Apr 2004 - Jan 2008
Senior Asic Engineer
Internet Machines Corp Apr 2000 - Apr 2004
Senior Asic Engineer
Motorola Apr 1996 - Apr 2000
Staff Engineer
E-Systems/Raytheon Sep 1992 - Apr 1996
Cca Lead Engineer

Education:

University of Connecticut 1990 - 1990
Bachelors, Bachelor of Science, Electronics Engineering

Skills:

Asic
Verilog
Systemverilog
Rtl Design
Fpga
Soc
High Speed Digital Design
Debugging
Ic
Digital Ic Design
Functional Verification
Open Verification Methodology
Rtl Coding
Rtl Verification
Timing Closure
Static Timing Analysis
Processors

Us Patents

Frequency Synthesis With Gapper
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US Patent:

20140266328, Sep 18, 2014
Filed:

Mar 18, 2013
Appl. No.:

13/846311
Inventors:

- Sunnyvale CA, US
Michael GROSNER - San Diego CA, US
Timothy P. WALKER - Boxford MA, US
Assignee:

APPLIED MICRO CIRCUITS CORPORATION - Sunnyvale CA
International Classification:

H03L 7/16
US Classification:

327115
Abstract:

Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the first integer divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

Method And Apparatus For Gapping
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US Patent:

20140266339, Sep 18, 2014
Filed:

Mar 18, 2013
Appl. No.:

13/846171
Inventors:

- Sunnyvale CA, US
Michael GROSNER - San Diego CA, US
Timothy P. WALKER - Boxford MA, US
Assignee:

APPLIED MICRO CIRCUITS CORPORATION - Sunnyvale CA
International Classification:

H03L 7/08
US Classification:

327156
Abstract:

Systems and methods for generating gapped signals comprising a Delta Sigma Modulator (DSM) configured to generate gapping control signals used to control gap removal rates of an associated gapping unit. The DSM is configured to generate a gapping control signal based on a value of an overflow resulted from performing adding a first number with a remainder of a stored value modulo a second number. The gap removal rates as well as the gap removal resolutions can be adjusted by selecting appropriate values of the first number, the stored value, and the second number. The gapping resolution can be a portion of a pulse. The first number and the second number may be derived from an intended frequency ratio between a gapped signal and a corresponding input signal. The gapping unit may comprise a gapping circuit or a multi-modulus divider.

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