Ming Jin

US Patent:

7754516, Jul 13, 2010

Filed:

Oct 6, 2008

Appl. No.:

12/287073

Inventors:

Ming Jin - San Jose CA, US
Ilya V. Karpov - Santa Clara CA, US
Jinwook Lee - San Jose CA, US
Narahari Ramanuja - Fremont CA, US

International Classification:

H01L 45/00

US Classification:

438 54, 257E45002, 438 95

Abstract:

A small critical dimension element, such as a heater for an ovonic unified memory, may be formed within a pore by using successive sidewall spacers. The use of at least two successive spacers enables the limitations imposed by lithography and the limitations imposed by bread loafing to be overcome to provide reduced critical dimension elements.

US Patent:

8026173, Sep 27, 2011

Filed:

Mar 13, 2008

Appl. No.:

12/048121

Inventors:

Ilya Karpov - Santa Clara CA, US
Yudong Kim - Cupertino CA, US
Ming Jin - San Jose CA, US
Shyam Prasad Teegapuram - Santa Clara CA, US
Jinwook Lee - San Jose CA, US

Assignee:

STMicroelectronics S.r.l. - Agrate Brianza

International Classification:

H01L 21/8239

US Classification:

438639, 257E21004, 257E2152, 438482, 438692, 438696, 438733

Abstract:

A phase change memory formed by a plurality of phase change memory devices having a chalcogenide memory region extending over an own heater. The heaters have all a relatively uniform height. The height uniformity is achieved by forming the heaters within pores in an insulator that includes an etch stop layer and a sacrificial layer. The sacrificial layer is removed through an etching process such as chemical mechanical planarization. Since the etch stop layer may be formed in a repeatable way and is common across all the devices on a wafer, considerable uniformity is achieved in heater height. Heater height uniformity results in more uniformity in programmed memory characteristics.

US Patent:

8067260, Nov 29, 2011

Filed:

Jun 3, 2010

Appl. No.:

12/792992

Inventors:

Ming Jin - San Jose CA, US
Ilya V. Karpov - Santa Clara CA, US
Jinwook Lee - San Jose CA, US
Narahari Ramanuja - Fremont CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 45/00

US Classification:

438 54, 257 3, 257E45002

Abstract:

A small critical dimension element, such as a heater for an ovonic unified memory, may be formed within a pore by using successive sidewall spacers. The use of at least two successive spacers enables the limitations imposed by lithography and the limitations imposed by bread loafing be overcome to provide reduced critical dimension elements.

US Patent:

8161351, Apr 17, 2012

Filed:

Mar 30, 2010

Appl. No.:

12/750654

Inventors:

Ming Jin - Fremont CA, US
Shaohua Yang - San Jose CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03M 13/00

US Classification:

714758

Abstract:

Various embodiments of the present invention provide systems and methods for preparing and accessing super sector data sets. As an example, a data storage system including a storage medium is disclosed. The storage medium includes a first servo data region and a second servo data region separated by a user data region. The user data region includes at least a portion of a first codeword and a portion of a second codeword that are together associated with a common header data.

US Patent:

8321755, Nov 27, 2012

Filed:

Mar 16, 2012

Appl. No.:

13/422742

Inventors:

Ming Jin - Fremont CA, US
Shaohua Yang - San Jose CA, US

Assignee:

LSI Corporation - Milpital CA

International Classification:

H03M 13/00

US Classification:

714758

Abstract:

Various embodiments of the present invention provide systems and methods for preparing and accessing super sector data sets. As an example, a data storage system including a storage medium is disclosed. The storage medium includes a first servo data region and a second servo data region separated by a user data region. The user data region includes at least a portion of a first codeword and a portion of a second codeword that are together associated with a common header data.

US Patent:

8379498, Feb 19, 2013

Filed:

Jul 19, 2011

Appl. No.:

13/186146

Inventors:

George Mathew - San Jose CA, US
Ming Jin - Fremont CA, US
Shaohua Yang - San Jose CA, US
Erich F. Haratsch - Bethlehem PA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G11B 5/09

US Classification:

369 4728, 360 51, 360 69

Abstract:

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a data buffer, an inter-track interference response circuit, an inter-track interference signal estimator circuit, and a sync mark detector circuit. The data buffer is operable to store a previous track data set that includes a first sync pattern. The inter-track interference response circuit is operable to estimate an inter-track interference response from the previous track data set based at least in part on the previous track data set and a current track data set. The current track data set includes a second sync pattern. The inter-track interference signal estimator circuit is operable to calculate an inter-track interference from the previous track data set based at least in part on the previous track data set and the inter-track interference response from the previous track data set. The sync mark detector circuit operable to identify the first sync pattern in the inter-track interference from the previous track data set in the current track data set.

US Patent:

8526133, Sep 3, 2013

Filed:

Jul 19, 2011

Appl. No.:

13/185562

Inventors:

Haitao Xia - San Jose CA, US
George Mathew - San Jose CA, US
Ming Jin - Fremont CA, US
Shaohua Yang - San Jose CA, US

Assignee:

LSI Corporation - San Jose CA

International Classification:

G11B 21/02

US Classification:

360 75, 360 55, 360 7812, 360 31

Abstract:

Various embodiments of the present invention provide systems and methods for calculating and/or modifying fly height. For example, a circuit for calculating fly height is disclosed that includes: a first pattern detector circuit, a second pattern detector circuit, a first pattern fly height calculation circuit, a second pattern fly height calculation circuit, a first averaging circuit, a second averaging circuit, and a combining circuit.

US Patent:

8539328, Sep 17, 2013

Filed:

Aug 19, 2011

Appl. No.:

13/213808

Inventors:

Ming Jin - Fremont CA, US
Fan Zhang - Milpitas CA, US
Wu Chang - Santa Clara CA, US

Assignee:

LSI Corporation - San Jose CA

International Classification:

G06F 7/02
H03M 13/00

US Classification:

714819

Abstract:

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a noise injection circuit. The noise injection circuit is operable to: determine a difference between a first data output and a second data output to yield an error; and augment an interim data with a noise value corresponding to the error to yield a noise injected output. The interim data may be either the first data output or the second data output.