Ming Jin - San Jose CA, US Ilya V. Karpov - Santa Clara CA, US Jinwook Lee - San Jose CA, US Narahari Ramanuja - Fremont CA, US
International Classification:
H01L 45/00
US Classification:
438 54, 257E45002, 438 95
Abstract:
A small critical dimension element, such as a heater for an ovonic unified memory, may be formed within a pore by using successive sidewall spacers. The use of at least two successive spacers enables the limitations imposed by lithography and the limitations imposed by bread loafing to be overcome to provide reduced critical dimension elements.
Semiconductor Structure, In Particular Phase Change Memory Device Having A Uniform Height Heater
Ilya Karpov - Santa Clara CA, US Yudong Kim - Cupertino CA, US Ming Jin - San Jose CA, US Shyam Prasad Teegapuram - Santa Clara CA, US Jinwook Lee - San Jose CA, US
A phase change memory formed by a plurality of phase change memory devices having a chalcogenide memory region extending over an own heater. The heaters have all a relatively uniform height. The height uniformity is achieved by forming the heaters within pores in an insulator that includes an etch stop layer and a sacrificial layer. The sacrificial layer is removed through an etching process such as chemical mechanical planarization. Since the etch stop layer may be formed in a repeatable way and is common across all the devices on a wafer, considerable uniformity is achieved in heater height. Heater height uniformity results in more uniformity in programmed memory characteristics.
Ming Jin - San Jose CA, US Ilya V. Karpov - Santa Clara CA, US Jinwook Lee - San Jose CA, US Narahari Ramanuja - Fremont CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 45/00
US Classification:
438 54, 257 3, 257E45002
Abstract:
A small critical dimension element, such as a heater for an ovonic unified memory, may be formed within a pore by using successive sidewall spacers. The use of at least two successive spacers enables the limitations imposed by lithography and the limitations imposed by bread loafing be overcome to provide reduced critical dimension elements.
Ming Jin - Fremont CA, US Shaohua Yang - San Jose CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H03M 13/00
US Classification:
714758
Abstract:
Various embodiments of the present invention provide systems and methods for preparing and accessing super sector data sets. As an example, a data storage system including a storage medium is disclosed. The storage medium includes a first servo data region and a second servo data region separated by a user data region. The user data region includes at least a portion of a first codeword and a portion of a second codeword that are together associated with a common header data.
Ming Jin - Fremont CA, US Shaohua Yang - San Jose CA, US
Assignee:
LSI Corporation - Milpital CA
International Classification:
H03M 13/00
US Classification:
714758
Abstract:
Various embodiments of the present invention provide systems and methods for preparing and accessing super sector data sets. As an example, a data storage system including a storage medium is disclosed. The storage medium includes a first servo data region and a second servo data region separated by a user data region. The user data region includes at least a portion of a first codeword and a portion of a second codeword that are together associated with a common header data.
Systems And Methods For Track To Track Phase Alignment
George Mathew - San Jose CA, US Ming Jin - Fremont CA, US Shaohua Yang - San Jose CA, US Erich F. Haratsch - Bethlehem PA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G11B 5/09
US Classification:
369 4728, 360 51, 360 69
Abstract:
Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a data buffer, an inter-track interference response circuit, an inter-track interference signal estimator circuit, and a sync mark detector circuit. The data buffer is operable to store a previous track data set that includes a first sync pattern. The inter-track interference response circuit is operable to estimate an inter-track interference response from the previous track data set based at least in part on the previous track data set and a current track data set. The current track data set includes a second sync pattern. The inter-track interference signal estimator circuit is operable to calculate an inter-track interference from the previous track data set based at least in part on the previous track data set and the inter-track interference response from the previous track data set. The sync mark detector circuit operable to identify the first sync pattern in the inter-track interference from the previous track data set in the current track data set.
Systems And Methods For User Data Based Fly Height Calculation
Haitao Xia - San Jose CA, US George Mathew - San Jose CA, US Ming Jin - Fremont CA, US Shaohua Yang - San Jose CA, US
Assignee:
LSI Corporation - San Jose CA
International Classification:
G11B 21/02
US Classification:
360 75, 360 55, 360 7812, 360 31
Abstract:
Various embodiments of the present invention provide systems and methods for calculating and/or modifying fly height. For example, a circuit for calculating fly height is disclosed that includes: a first pattern detector circuit, a second pattern detector circuit, a first pattern fly height calculation circuit, a second pattern fly height calculation circuit, a first averaging circuit, a second averaging circuit, and a combining circuit.
Systems And Methods For Noise Injection Driven Parameter Selection
Ming Jin - Fremont CA, US Fan Zhang - Milpitas CA, US Wu Chang - Santa Clara CA, US
Assignee:
LSI Corporation - San Jose CA
International Classification:
G06F 7/02 H03M 13/00
US Classification:
714819
Abstract:
Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a noise injection circuit. The noise injection circuit is operable to: determine a difference between a first data output and a second data output to yield an error; and augment an interim data with a noise value corresponding to the error to yield a noise injected output. The interim data may be either the first data output or the second data output.
Coupang
Principal Software Engineer
Paypal Jan 2013 - Jul 2018
Member of Technical Staff
Deem, Inc. Oct 2008 - Jan 2013
Senior Software Engineer
Gemini Mobile Technologies Dec 2005 - Nov 2007
Senior Software Engineer
Samsung Jan 2004 - Nov 2005
Software Engineer
Education:
Cornell University
Bachelors, Bachelor of Science, Computer Science
Skills:
Java Mobile Devices Software Engineering Agile Methodologies Jsp Software Development Web Services Java Enterprise Edition Xml Javascript Saas C++ Enterprise Software Sql System Architecture Product Management Wireless
Intel Corporation
Foundry Program Manager
Intel Corporation Oct 1995 - Jun 2005
Senior Process Engineer
Nortel Jul 1993 - Sep 1995
Process Development Engineer
Education:
Tsing Hua University In Beijing, China
Skills:
Product Management Semiconductors Cmos Ic R&D Spc Cross Functional Team Leadership Semiconductor Industry Failure Analysis Engineering Engineering Management
Semiconductors Asic Signal Processing Soc Debugging Storage Verilog Embedded Systems C Matlab Simulations Algorithms Failure Analysis Fpga Characterization Testing Firmware Magnetic Recording System Architecture Hardware Architecture System on A Chip Python
Hong Kong University of Science and Technology - Electrical Engineering, University of California, Berkeley - Electrical Engineering & Computer Science
About:
Present research interests in energy-efficient buildings, data mining and statistical modeling of massive data to reveal crucial information of patterns and trends. Also interested in the integration ...
Ming Jin
Work:
Amandatour.com CENTRO IMPIEGO PRATO CONFARTIGIANATO