Naoyoshi J Kusaba

US Patent:

8298907, Oct 30, 2012

Filed:

Dec 12, 2011

Appl. No.:

13/323033

Inventors:

Herbert L. Ho - New Windsor NY, US
Naoyoshi Kusaba - Hopewell Junction NY, US
Karen A. Nummy - Newburgh NY, US
Carl J. Radens - Lagrangeville NY, US
Ravi M. Todi - Poughkeepsie NY, US
Geng Wang - Stormville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/20

US Classification:

438386, 438589, 257E21158, 257E21646

Abstract:

A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i. e. , SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.

US Patent:

8642440, Feb 4, 2014

Filed:

Oct 24, 2011

Appl. No.:

13/279877

Inventors:

Chengwen Pei - Hopewell Junction NY, US
Herbert Lei Ho - Hopewell Junction NY, US
Naoyoshi Kusaba - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/20

US Classification:

438386, 438957

Abstract:

An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance.

US Patent:

20090072355, Mar 19, 2009

Filed:

Sep 17, 2007

Appl. No.:

11/856260

Inventors:

Kangguo Cheng - Beacon NY, US
Lisa F. Edge - State College PA, US
Johnathan E. Faltermeier - Fishkill NY, US
Naoyoshi Kusaba - Hopewell Junction NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/06
H01L 21/311

US Classification:

257622, 438702, 257E21249, 257E29005

Abstract:

A protective dielectric layer is formed on a first shallow trench having straight sidewalls, while exposing a second shallow trench. An oxidation barrier layer is formed on the semiconductor substrate. A resist is applied and recessed within the second shallow trench. The oxidation barrier layer is removed above the recessed resist. The resist is removed and thermal oxidation is performed so that a thermal oxide collar is formed above the remaining oxidation mask layer. The oxidation barrier layer is thereafter removed and exposed semiconductor area therebelow depth is etched to form a bottle shaped shallow trench. The first and the bottle shaped trenches are filled with a dielectric material to form a straight sidewall shallow trench isolation structure and a bottle shallow trench isolation structure, respectively. Both shallow trench isolation structures may be employed to provide optimal electrical isolation and device performance to semiconductor devices having different depths.

US Patent:

20090104776, Apr 23, 2009

Filed:

Oct 18, 2007

Appl. No.:

11/874392

Inventors:

David M. Dobuzinsky - New Windsor NY, US
Johnathan E. Faltermeier - Delanson NY, US
Naoyoshi Kusaba - Hopewell Junction NY, US
Joyce C. Liu - Carmel NY, US
Munir D. Naeem - Poughkeepsie NY, US
Siddhartha Panda - Kanpur, IN
Richard S. Wise - Newburgh NY, US
Hongwen Yan - Somers NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 21/4763

US Classification:

438684, 257E21495

Abstract:

A method for forming lines for semiconductor devices including, depositing a shallow trench isolation (STI) film stack on a silicon substrate, depositing a layer of polysilicon on the STI film stack, depositing a layer of antireflective coating on the layer of polysilicon, developing a phototoresist on the antireflective coating, wherein the photoresist defines a line, etching the layer of antireflective coating and the layer of polysilicon using RIE with a low bias power, removing the photoresist, removing the layer of antireflective coating, etching the STI film stack to form the line, wherein the layer of polysilicon further defines the line.

US Patent:

20110042731, Feb 24, 2011

Filed:

Aug 21, 2009

Appl. No.:

12/545116

Inventors:

Herbert L. Ho - Hopewell Junction NY, US
Naoyoshi Kusaba - Hopewell Junction NY, US
Karen A. Nummy - Hopewell Junction NY, US
Carl J. Radens - Hopewell Junction NY, US
Ravi M. Todi - Hopewell Junction NY, US
Geng Wang - Hopewell Junction NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 27/108
H01L 21/28
H01L 21/8242

US Classification:

257296, 438589, 438386, 257E21646, 257E21158, 257E27084

Abstract:

A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.

US Patent:

20120175694, Jul 12, 2012

Filed:

Feb 29, 2012

Appl. No.:

13/408187

Inventors:

Herbert L. Ho - New Windsor NY, US
Naoyoshi Kusaba - Hopewell Junction NY, US
Karen A. Nummy - Newburgh NY, US
Carl J. Radens - LaGrangeville NY, US
Ravi M. Todi - Poughkeepsie NY, US
Geng Wang - Stormville NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 27/108

US Classification:

257301, 257E27084

Abstract:

A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

US Patent:

20130093043, Apr 18, 2013

Filed:

Oct 17, 2011

Appl. No.:

13/274389

Inventors:

Naoyoshi KUSABA - Hopewell Junction NY, US
Oh-jung KWON - Hopewell Junction NY, US
Zhengwen LI - Danbury CT, US
Hongwen YAN - Somers NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/02
H01L 21/302

US Classification:

257508, 438427, 257E21214, 257E29002

Abstract:

An array or moat isolation structure for eDRAM and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.

US Patent:

20150279843, Oct 1, 2015

Filed:

Jun 11, 2015

Appl. No.:

14/736695

Inventors:

- Armonk NY, US
Naoyoshi Kusaba - Hopewell Junction NY, US
Karen A. Nummy - Newburgh NY, US
Carl J. Radens - LaGrangeville NY, US
Ravi M. Todi - San Diego CA, US
Geng Wang - Stormville NY, US

International Classification:

H01L 27/108

Abstract:

A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.