Narayanan Ramanan from San Jose, CA, age 38

Nand Sensing Circuit And Technique For Read-Disturb Mitigation
view source
US Patent:

20220293193, Sep 15, 2022
Filed:

Mar 15, 2021
Appl. No.:

17/202133
Inventors:

- Santa Clara CA, US
Narayanan RAMANAN - San Jose CA, US
International Classification:

G11C 16/26
G11C 16/04
G11C 16/24
G11C 16/34
G06F 3/06
Abstract:

Sensing circuits and techniques for NAND memory that can enable improved read disturb on the selected SGS are described herein. In one example, a reverse sensing circuit includes circuitry coupled with a bitline of the string of NAND memory cells to perform a sensing operation. The circuitry charges the bitline of the string of NAND memory cells to a target bitline voltage and applies a voltage to the source line that is higher than the bitline voltage. The sense current flows through the string from the source line to the bitline. The voltage at a sensing node that is indicative of a threshold voltage of a memory cell can then be detected.

Modulation Of Source Voltage In Nand-Flash Array Read
view source
US Patent:

20220293194, Sep 15, 2022
Filed:

Mar 15, 2021
Appl. No.:

17/202137
Inventors:

- Santa Clara CA, US
Narayanan RAMANAN - San Jose CA, US
International Classification:

G11C 16/26
G11C 16/04
G11C 16/08
G11C 16/30
G11C 16/34
Abstract:

Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source voltage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle.

Method And Apparatus To Mitigate Hot Electron Read Disturbs In 3D Nand Devices
view source
US Patent:

20220284968, Sep 8, 2022
Filed:

May 26, 2022
Appl. No.:

17/825960
Inventors:

- Santa Clara CA, US
Richard M. Fastow - Cupertino CA, US
Xuehong Yu - San Jose CA, US
Xin Sun - Fremont CA, US
Hyungseok Kim - San Jose CA, US
Narayanan Ramanan - San Jose CA, US
Amol R. Joshi - Sunnyvale CA, US
Krishna Parat - Palo Alto CA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G11C 16/16
G11C 16/26
G11C 16/04
G11C 16/32
G11C 16/08
Abstract:

An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

Dynamic Detection And Dynamic Adjustment Of Sub-Threshold Swing In A Memory Cell Sensing Circuit
view source
US Patent:

20220208286, Jun 30, 2022
Filed:

Dec 24, 2020
Appl. No.:

17/134010
Inventors:

- Santa Clara CA, US
Shantanu R. RAJWADE - Santa Clara CA, US
Matin AMANI - Fremont CA, US
Narayanan RAMANAN - San Jose CA, US
International Classification:

G11C 16/34
G11C 16/08
G11C 16/30
G11C 16/10
G11C 16/26
Abstract:

For a nonvolatile (NV) storage media such as NAND media that is written by a program and program verify operation, the system can determine an expected number of SSPC (selective slow programming convergence) cells for a page of cells for specific conditions of the page. The system can perform program verify with a first wordline (WL) select voltage for SSPC cell detection for a first write of the page to detect the expected number of SSPC cells. Based on the determined expected number of SSPC cells, the system can set a boost voltage to capture an expected number of SSPC cells during the program verify operation. The system performs program verify for subsequent writes to the page with a higher WL select voltage, to perform program verify for standard cells and then SSPC program verify with the boost voltage determined from the first write.

Program Verify Process Having Placement Aware Pre-Program Verify (Ppv) Bucket Size Modulation
view source
US Patent:

20220366991, Nov 17, 2022
Filed:

May 14, 2021
Appl. No.:

17/321114
Inventors:

- Santa Clara CA, US
Tarek Ahmed AMEEN BESHARI - Santa Clara CA, US
Matin AMANI - Fremont CA, US
Narayanan RAMANAN - San Jose CA, US
Arun THATHACHARY - Santa Clara CA, US
International Classification:

G11C 16/34
G06F 3/06
Abstract:

An apparatus is described. An apparatus includes controller logic circuitry to perform a program-verify programming process to a flash memory chip. The program-verify programming process is to reduce a size of a pre-program verify (PPV) bucket in response to a number of cells being fully programmed to a same digital state. The number of cells are less than a total number of cells to be programmed to the same digital state.

Device, System, And Method To Verify Data Programming Of A Multi-Level Cell Memory Based On One Of Temperature, Pressure, Wear Condition Or Relative Position Of The Memory Cell
view source
US Patent:

20210257036, Aug 19, 2021
Filed:

Feb 13, 2020
Appl. No.:

16/790074
Inventors:

- Santa Clara CA, US
Tarek Ahmed Ameen Beshari - Santa Clara CA, US
Narayanan Ramanan - San Jose CA, US
Arun Thathachary - Santa Clara CA, US
Shantanu Rajwade - San Mateo CA, US
Matin Amani - Fremont CA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G11C 16/34
G11C 11/56
G11C 16/10
G11C 16/30
G11C 16/26
Abstract:

Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array.

Program Verify Technique For Non-Volatile Memory
view source
US Patent:

20200342946, Oct 29, 2020
Filed:

Apr 26, 2019
Appl. No.:

16/396478
Inventors:

- Santa Clara CA, US
Richard FASTOW - Cupertino CA, US
Krishna K. PARAT - Palo Alto CA, US
Arun THATHACHARY - Santa Clara CA, US
Narayanan RAMANAN - San Jose CA, US
International Classification:

G11C 16/34
G11C 16/04
G11C 16/08
Abstract:

A technique for read or program verify (PV) operations for non-volatile memory is described. In one example, at the end of a program verify operation (e.g., during a program verify recovery phase), a number of wordlines near a selected wordline are ramped down one at a time. Ramping down wordlines near the selected wordline one at a time can significantly reduce the trapped charge in the channel, enabling lower program disturb rates and improved threshold voltage distributions. In one example, the same technique of ramping down wordlines near the selected wordline can be applied to a read operation.