Patrick W Gannon

US Patent:

41492455, Apr 10, 1979

Filed:

Jun 9, 1977

Appl. No.:

5/805065

Inventors:

Patrick M. Gannon - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1306
G06F 918

US Classification:

364200

Abstract:

The described embodiment provides storage control (PSCF) for overlapping the handling of processor store requests between their generation by an instruction execution means (IPPF) and their presentation to system main storage (MS). The embodiment uses a store counter, an inpointer counter, an outpointer counter, a translator pointer register, an output counter and a plurality of registers sets to process and control the sequencing of all store requests so that the PSCF can output them to MS in the order received from the IPPF. The embodiment uses the counters to coordinate the varying delays in PSCF processing of plural store request contained in different register sets and the translator. The store counter obtains independence between plural IPPF operand address (OA) registers which send the store requests and plural PSCF register sets which handle the store request. The number of OA registers is made independent of the number of register sets.

US Patent:

41363850, Jan 23, 1979

Filed:

Mar 24, 1977

Appl. No.:

5/781022

Inventors:

Patrick M. Gannon - Poughkeepsie NY
Andrew R. Heller - Mohegan Lake NY
Ronald M. Smith - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

364200

Abstract:

The embodiments relate to special controls in a processor which eliminate synonym entries in a translation lookaside buffer (DLAT) for a system which has DLAT entries that can concurrently translate virtual addresses in multiple address spaces into real main storage addresses. The controls provide a common space bit in any segment table entry (STE) or alternatively in any page table entry (PTE) in any private address space to indicate whether the segment or page, respectively, contains programs and data private to the address space or shared by all address spaces. Each DLAT entry contains a common/private storage indictor which is set to the state of the common space bit in the STE or PTE used in an address translation loaded into the DLAT entry. When the entry is read, the private/common storage indicator controls whether the DLAT can only be used by the address space identified in the DLAT, or by all address spaces.

US Patent:

41575865, Jun 5, 1979

Filed:

May 5, 1977

Appl. No.:

5/794323

Inventors:

Patrick M. Gannon - Poughkeepsie NY
Julius D. Jones - Unionvale NY
Dale M. Junod - Highland NY
Richard L. Partridge - Wappingers Falls NY
Thomas R. Wright - Shokan NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 702

US Classification:

364200

Abstract:

This specification relates to performance of partial store operation in a hierarchical memory system which has a buffer store interposed between a processor interrogating the memory system and the main memory of the memory system. Such a partial store operation can be performed on a word of data in the main memory using the buffer store copy of that word of data. The copy of the word of data is read out of the buffer store into a register where it is modified to form a new word by replacing one or more but not all of the bytes in the word of data with bytes supplied by the processor. The new word is then placed in the main memory by performing a full store operation. The problem with performing a partial store operation in this manner is that the copy of the word of data in the buffer store may not be up-to-date. A technique is provided to eliminate the possibility of this old data being rewritten back into the main memory.

US Patent:

46959505, Sep 22, 1987

Filed:

Sep 17, 1984

Appl. No.:

6/651491

Inventors:

Henry R. Brandt - Poughkeepsie NY
Patrick M. Gannon - Poughkeepsie NY
Wan L. Leung - Coral Springs FL
Timothy R. Marchini - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1210

US Classification:

364200

Abstract:

A unique high-speed hardware arrangement for generating double-level address translations in combination a translation look-aside buffer (TLB) structure that can store and lookup intermediate translations during a double-level translation. The hardware proceeds to the completion of a double-level translation without having to backup its operation, although an intermediate TLB miss is encountered, without danger of CPU deadlock occurring. The hardware arrangement also performs all single-level address translations required by the system.

US Patent:

52652327, Nov 23, 1993

Filed:

Apr 3, 1991

Appl. No.:

7/679900

Inventors:

Patrick M. Gannon - Poughkeepsie NY
Michael Ignatowski - Red Hook NY
Matthew A. Krygowski - Hopewell Junction NY
Lishing Liu - Pleasantville NY
Donald W. Price - Lake Katrine NY
William K. Rodiger - Sudbury NY
Gregory Salyer - Woodstock NY
Yee-Ming Ting - Cornwall NY
Michael P. Witt - Fishkill NY

Assignee:

International Business Machines Corporation - NY

International Classification:

G06F 1300

US Classification:

395425

Abstract:

A coherence directory and its methods of operation are disclosed for private processor caches in a multiple processor system to control data coherence in the system. It provides cross-invalidate (XI) controls for the assignment of exclusive and public ownership to data units in the processor caches, including required cross-invalidation of data units among the processor caches to obtain data coherence in the system in an efficient manner. The coherence directory can be used in a multiple processor system with or without any shared second level (L2) cache, shared or private. When a shared L2 cache is used to improve system access time, the coherence directory can also be used as the second level directory for the shared L2 cache and eliminate the need for any additional L2 directory(s).

US Patent:

41897706, Feb 19, 1980

Filed:

Mar 16, 1978

Appl. No.:

5/887097

Inventors:

Patrick M. Gannon - Poughkeepsie NY
John S. Liptay - Rhinebeck NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 100

US Classification:

364200

Abstract:

In the case of a cache miss, the successive fetch requests by the I-unit for sublines (e. g. doublewords) of a variable length field operand are provided by the first through the highest-address fetched sublines in a line being accessed from main storage via a cache bypass. This avoids the time delay for the I-unit caused by waiting until the complete line has been transferred to the cache before all required sublines in the line are obtainable from the cache. Address operand pairs (AOP's) consisting of request and buffer registers are provided in the I-unit to handle the fetched sublines as fast as the cache bypass can provide them from main storage. If there is a cache hit, the sublines are accessed from the cache.

US Patent:

53177053, May 31, 1994

Filed:

Aug 26, 1993

Appl. No.:

8/112174

Inventors:

Patrick M. Gannon - Poughkeepsie NY
Peter H. Gum - Poughkeepsie NY
Roger E. Hough - Highland NY
Robert E. Murray - Woodstock NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1202

US Classification:

395400

Abstract:

A system for reducing purging of a translation lookaside buffer (TLB) to reduce operating system overhead in a system running multiple levels of virtual machines. A system typically must purge TLB entries whenever an underlying page table entry is invalidated due to paging activity on the host machine, or an underlying guest machine. A system for reducing the number of cases in which guest translations are based on host page table entries is provided. Additional logic is supplied to analyze each invalidate page table entry (IPTE) instruction to minimize the extent of purging required as a result of that instruction. When the region relocate facility is in operation, or when no pageable TLB's have been constructed, only the entry corresponding to the page table entry to be invalidated need be purged. This limited purging reduces the overhead by reducing the time spent in purging and the time required in address translation to rebuild the TLB. This time saving results in increased performance in systems with multi-level guests.

Author:

Patrick Gannon

ISBN #:

0070153078

Author:

Patrick Gannon

ISBN #:

0072130733