Paul A Niekrewicz

US Patent:

8549330, Oct 1, 2013

Filed:

Dec 18, 2009

Appl. No.:

12/641578

Inventors:

Paul Niekrewicz - Essex Junction VT, US
Pascal A. Nsame - Essex Junction NY, US
Aydin Suren - Essex Junction VT, US
Sebastian Ventrone - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/00

US Classification:

713300, 713310, 713320, 713321, 713322, 713323, 713324, 713330, 713340

Abstract:

A computer system with reliable dynamic energy management includes a thread synchronized energy configurator, the thread synchronized energy configurator extending an instruction decoder of the computer system and the thread synchronized energy configurator is disposed to append an energy configuration field including energy configuration bits to pipeline control bits of instructions in the instruction decoder, a thread synchronized dynamic frequency shifter (DFS), the thread synchronized DFS disposed to set control signals indicative of a frequency shift both per thread and per pipeline, and a thread synchronized general purpose register (GPR) super scaler, wherein the GPR super scaler is disposed to optimize thread operation based upon the set control signals.

US Patent:

20090201394, Aug 13, 2009

Filed:

Feb 7, 2008

Appl. No.:

12/027283

Inventors:

Phillip L. Corson - Westford VT, US
Mete Erturk - Alburg VT, US
Ezra D.B. Hall - Richmond VT, US
Paul A. Niekrewicz - Essex Junction VT, US

International Classification:

H04N 5/335

US Classification:

348294, 348E05091

Abstract:

Disclosed are embodiments of a pixel imaging circuit that incorporates a standard photodiode. However, the imaging circuit is modified with a feedback loop to provide a first photo response over a first portion of the light sensing range (e.g., at higher light intensity range) and a second reduced-sensitivity photo response over a second portion of the light sensing range (i.e., at a lower light intensity range), thereby extending the circuits dynamic range of coverage. Also disclosed are embodiments of an associated imaging method and a design structure that is embodied in a machine readable medium and used in the imaging circuit design process.

US Patent:

20130074033, Mar 21, 2013

Filed:

Sep 16, 2011

Appl. No.:

13/234275

Inventors:

Ezra D. HALL - Richmond VT, US
Paul A. NIEKREWICZ - Essex Junction VT, US
Rohit SHETTY - Essex Junction VT, US
Aydin SUREN - Essex Junction VT, US
Sebastian T. VENTRONE - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 3/048
G06F 9/44

US Classification:

717109, 715771

Abstract:

System and computer-implemented methods herein design a configurable pipelined processor. Such systems and methods provide a configuration specification, by providing a base processor or digital design description, a base instruction set with a plurality of base instructions, and a plurality of configurable features. At least one of the configurable features is an additional instruction different from the base instructions. Further, such systems and methods generate a hardware implementation based on the configuration specification to produce a plurality of configured pipeline stages. The configured pipeline stages are different from base pipeline stages in a base processor or digital design hardware implementation (corresponding to the base processor or digital design description as a result of the additional instruction being included in the configuration specification). Such systems and methods also generate, based on the configuration specification, a plurality of software development tools including an application program compiler.

US Patent:

20140195771, Jul 10, 2014

Filed:

Jan 4, 2013

Appl. No.:

13/734218

Inventors:

- Armonk NY, US
Paul A Niekrewicz - Essex Junction VT, US
Aydin Suren - Essex Junction VT, US
Sebastian T. Ventrone - South Burlington VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 12/10

US Classification:

711205, 711204

Abstract:

In a particular embodiment, a method of anticipatorily loading a page of memory is provided. The method may include, during execution of first program code using a first page of memory, collecting data for at least one attribute of the first page of memory, including collecting data about at least one next page of memory that interacts with the first page of memory for a historical topology attribute of the first page of memory. The method may also include, during execution of second program code using the first page of memory, determining a second page of memory to anticipatorily load based on the historical topology attribute of the first page of memory.