Peter G Capek from 210 Illington Rd, Crotonville, NY 10562, age 76, Phone: 9147625542

Name / Title

Company / Classification

Phones & Addresses

Peter Capek
President

OSSINING CHIROPRACTIC OFFICE, PC
Chiropractor

71 Croton Ave, Ossining, NY 10562
9149411141

Us Patents

Symmetric Multi-Processing System With Attached Processing Units Being Able To Access A Shared Memory Without Being Structurally Configured With An Address Translation Mechanism
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US Patent:

6779049, Aug 17, 2004
Filed:

Dec 14, 2000
Appl. No.:

09/736585
Inventors:

Erik R. Altman - Danbury CT
Peter G. Capek - Ossining NY
Michael Gschwind - Chappaqua NY
Harm Peter Hofstee - Austin TX
James Allan Kahle - Austin TX
Ravi Nair - Briarcliff Manor NY
Sumedh Wasudeo Sathaye - Lagrangeville NY
John-David Wellman - Hopewell Junction NY
Masakazu Suzuoki - Austin TX
Takeshi Yamazaki - Austin TX
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 1328
US Classification:

710 22, 710 26, 711147, 711153, 711173, 711202, 711203, 711205, 711206, 711207, 711208
Abstract:

A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Symmetric Multi-Processing System Utilizing A Dmac To Allow Address Translation For Attached Processors
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US Patent:

6907477, Jun 14, 2005
Filed:

Feb 19, 2004
Appl. No.:

10/782044
Inventors:

Erik R. Altman - Danbury CT, US
Peter G. Capek - Ossining NY, US
Michael Gschwind - Yorktown NY, US
Harm Peter Hofstee - Austin TX, US
James Allan Kahle - Austin TX, US
Ravi Nair - Briarcliff Manor NY, US
Sumedh Wasudeo Sathaye - Fishkill NY, US
John-David Wellman - Peekskill NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F013/28
G06F013/368
G06F009/28
US Classification:

710 22, 710 26, 711147, 711153, 711173, 711202, 711203, 711205, 711206, 711207, 711208
Abstract:

A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Method And System For Maintaining Coherency In A Multiprocessor System By Broadcasting Tlb Invalidated Entry Instructions
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US Patent:

6970982, Nov 29, 2005
Filed:

Oct 1, 2003
Appl. No.:

10/676540
Inventors:

Erik R. Altman - Danbury CT, US
Peter G. Capek - Ossining NY, US
Michael Karl Gschwind - Yorktown NY, US
Harm Peter Hofstee - Austin TX, US
James Allan Kahle - Austin TX, US
Ravi Nair - Briarcliff Manor NY, US
Sumedh Wasudeo Sathaye - Fishkill NY, US
John-David Wellman - Peekskill NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F013/00
US Classification:

711141, 711146, 711124, 709213
Abstract:

A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

System And Method For Obtaining Items At A Traveler's Destination
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US Patent:

7219074, May 15, 2007
Filed:

May 14, 2001
Appl. No.:

09/854613
Inventors:

Peter G. Capek - Ossining NY, US
Dimitri Kanevsky - Ossining NY, US
Sara H. Basson - White Plains NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06Q 30/00
US Classification:

705 26, 206534
Abstract:

A method for providing a service for a traveler to acquire at least one item at the traveler's destination, comprising the steps of receiving a request from a traveler for obtaining at least one item; providing the traveler with the option to one of rent and purchase the at least one item, arranging for the at least one item to be supplied, arranging for shipping of the at least one item to a location selected by the traveler at a time selected by the traveler; and conducting a transaction with the traveler for obtaining the at least one item.

Event Scheduling With Optimization
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US Patent:

7343312, Mar 11, 2008
Filed:

Apr 25, 2002
Appl. No.:

10/133721
Inventors:

Peter George Capek - Ossining NY, US
William Grey - Millwood NY, US
Paul Andrew Moskowitz - Yorktown Heights NY, US
Clifford A. Pickover - Yorktown Heights NY, US
Dailun Shi - Croton on Hudson NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 9/46
US Classification:

705 8, 705 9, 705 1
Abstract:

The present invention is a method for scheduling an event or meeting consisting of a plurality of persons which is determined by optimizing one or more variables. In the preferred embodiment, one or more requests for a meeting are pooled. A selected variable is optimized and an event is scheduled on the optimized variable. As additional meeting requests are pooled which conflict with the initial optimized event, the selected variable is again optimized and the event is dynamically rescheduled based on the optimized variable.

Method For Simd-Oriented Management Of Register Maps For Map-Based Indirect Register-File Access
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US Patent:

7360063, Apr 15, 2008
Filed:

Mar 2, 2006
Appl. No.:

11/366884
Inventors:

Peter G. Capek - Ossining NY, US
Jeffrey H. Derby - Chapel Hill NC, US
Robert K. Montoye - Austin TX, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 9/35
US Classification:

712217, 712 22
Abstract:

A facility is provided for managing register maps for map-based indirect register file access within a processor. The management facility includes a register mapping including a set of maps, each map of the set of maps having a plurality of map registers. A set of actual registers is indirectly accessed by the processor via map entries of the set of maps. The number of actual registers in the set of actual registers is greater than the number of map entries in the set of maps, and the map entries of the set of maps reference only a subset of the set of actual registers at any given time. The facility includes managing updates to multiple entries of the set of maps of the register mapping by updating multiple map entries of at least one map of the set of maps responsive to executing a single update instruction.

Non-Homogeneous Multi-Processor System With Shared Memory
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US Patent:

7509457, Mar 24, 2009
Filed:

Feb 24, 2005
Appl. No.:

11/065537
Inventors:

Erik Richter Altman - Danbury CT, US
Peter George Capek - Ossining NY, US
Michael Karl Gschwind - Chappaqua NY, US
Charles Ray Johns - Austin TX, US
Harm Peter Hofstee - Austin TX, US
Martin E. Hopkins - Bronxville NY, US
James Allan Kahle - Austin TX, US
Sumedh W. Sathaye - Cary NC, US
John-David Wellman - Hopewell Junction NY, US
Ravi Nair - Briarcliff Manor NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 12/00
US Classification:

711119, 711147, 711150
Abstract:

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

System For Simd-Oriented Management Of Register Maps For Map-Based Indirect Register-File Access
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US Patent:

7631167, Dec 8, 2009
Filed:

Jan 15, 2008
Appl. No.:

12/014335
Inventors:

Peter G. Capek - Ossining NY, US
Jeffrey H. Derby - Chapel Hill NC, US
Robert K. Montoye - Austin TX, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 9/35
US Classification:

712217, 712 22
Abstract:

A facility is provided for managing register maps for map-based indirect register file access within a processor. The management facility includes a register mapping including a set of maps, each map of the set of maps having a plurality of map registers. A set of actual registers is indirectly accessed by the processor via map entries of the set of maps. The number of actual registers in the set of actual registers is greater than the number of map entries in the set of maps, and the map entries of the set of maps reference only a subset of the set of actual registers at any given time. The facility includes managing updates to multiple entries of the set of maps of the register mapping by updating multiple map entries of at least one map of the set of maps responsive to executing a single update instruction.