Robert S Goeb

US Patent:

46334874, Dec 30, 1986

Filed:

Jan 17, 1985

Appl. No.:

6/691978

Inventors:

Robert Goeb - Spotswood NJ
Nathaniel L. Silber - Cedar Grove NJ

Assignee:

ITT Corporation - New York NY

International Classification:

H04L 704

US Classification:

375118

Abstract:

There is disclosed an automatic phasing network which network receives a data signal and synchronous timing signals. Initially, these signals are in an arbitrary but fixed phase relationship to one another. The circuit establishes a fixed phase relationship between the data and timing signals with a large degree of resistance of phase jitter. In order to accomplish these results, the circuit operates to select the edge of the clock signals which is farthest from given data transitions and uses this edge to produce a data signal which is synchronized to the timing signal. The circuit provides an accurate phase relationship between the data and timing signals for various out-of-phase conditions as where the data transitions lag the rising edge of the clock by angles which vary between -45 degrees to +315 degrees.

US Patent:

46022236, Jul 22, 1986

Filed:

Dec 5, 1984

Appl. No.:

6/678449

Inventors:

Robert Goeb - Spotswood NJ
Luis M. Gaspar - North Arlington NJ

Assignee:

ITT Corporation - New York NY

International Classification:

H03K 702
H03K 902

US Classification:

332 9R

Abstract:

A modulator circuit produces an AM modulated output signal by modulating a low rate digital signal on a higher rate data signal. The modulator circuit operates to switch the ground return of a line driver circuit which selectively amplifies the high rate data signal and has its ground return switched in accordance with the lower rate digital signal to produce an output modulated signal of a three level modulation characteristic whereby the modulation index of the signal is selectable by varying the impedance in series with the ground return of the line driver. A demodulator for the output signal of the modulator incorporates circuitry by which the high speed data carrier signal is first retrieved and is then subtracted from the modulated signal to yield a separate high speed data signal and the low speed digital signal with an enhanced signal-to-noise ratio.

US Patent:

47529261, Jun 21, 1988

Filed:

Oct 1, 1986

Appl. No.:

6/913917

Inventors:

Robert Goeb - Middlesex NJ

Assignee:

ITT Defense Communications, a division of ITT Corporation - Nutley NJ

International Classification:

H04B 900

US Classification:

370119

Abstract:

A orderwire detector circuit operates to identify whether an orderwire signal is of a digital or of an analog format. The orderwire signal is conveniently combined with a high speed data signal. The circuit operates to filter the high speed data signal from the orderwire signal and then square and retime the orderwire signal by means of a stable clock source. The orderwire signal is delayed by one bit and these bits are then compared to determine whether or not over a long period a certain voltage exists. If the proper voltage level exists after a plurality of samples, then it is assumed that the orderwire signal is a digital signal. Depending on the voltage detected, at the end of a predetermined sampling period, one can therefore discriminate between a signal orderwire signal or a analog orderwire signal.

US Patent:

47363592, Apr 5, 1988

Filed:

May 6, 1986

Appl. No.:

6/860374

Inventors:

Stuart B. Cohen - Cedar Grove NJ
Robert Goeb - Spotswood NJ
Ernest J. Oliveira - Livingston NJ

Assignee:

ITT Defense Communications , a division of ITT Corporation - Nutley NJ

International Classification:

H04B 900

US Classification:

370 3

Abstract:

A single fiber optical communication system (SFOCS) allows, in many operational scenarios, one-person deployment and recovery of optical links. Wavelength division multiplexing (WDM) is employed to provide full-duplex, bi-directional transmission. An optical subsystem achieves the wavelength multiplexing and demultiplexing while at the same time allowing for an unpolarized terminal design. Selection by the system of the WDM operating wavelengths between a pair of SFOCS terminals is performed without operator intervention.

US Patent:

62123653, Apr 3, 2001

Filed:

Jun 18, 1998

Appl. No.:

9/099716

Inventors:

Robert Goeb - Fort Wayne IN

Assignee:

ITT Manufacturing Enterprises, Inc. - Wilmington DE

International Classification:

H04M 1100

US Classification:

455 78

Abstract:

There is disclosed a circuit for selectively enabling communications by providing an output signal voltage of a first level indicative of a first transmission state and a second level corresponding to a second non-transmission state, the circuit having an FET having a gate, source, and drain, the source coupled to a first controlling means for providing a voltage Vs to the source, the drain coupled to an output terminal of the circuit for providing the output signal, and the gate coupled to a second control means for providing a voltage Vg to the gate, the FET operable in a first conducting mode when a gate to source voltage Vgs exceeds a predetermined threshold, indicative of a non-zero crossing amplitude region of an input voltage signal, to cause the output signal voltage to be at the second level corresponding to the non-transmission state, and in a second non-conducting mode, wherein the Vgs of the FET is less than the threshold, indicative of a zero-crossing of the input signal, for causing the output signal voltage to go to the first level, indicative of the transmission state, wherein the first and second control means responsive to the input voltage signal operate to vary the FET gate to source voltage and route current through the circuit to cause the FET to operate in the conducting and non-conducting modes.

US Patent:

49813714, Jan 1, 1991

Filed:

Feb 17, 1989

Appl. No.:

7/312508

Inventors:

Richard J. Gurak - Summit NJ
Robert Goeb - Spotswood NJ

Assignee:

ITT Corporation - New York NY

International Classification:

H04L 900
H04M 1106

US Classification:

380 49

Abstract:

An integrated I/O interface for a communication terminal, connectable with an external analog communication device and with an external digital communication device, includes an I/O interface subsystem having analog and digital arrays, a first connector for connecting the I/O interface subsystem to a digital processor for the terminal, and a second connector for connecting the I/O interface subsystem to both the analog communication device and the digital communication device. The digital array and the analog array including a CODEC are mounted on a platform carrier on the I/O interface subsystem board. The second connector is a single connector having pins for transmitting the analog signals, pins for the digital signals, a pin indicating whether the analog or digital mode is selected, and a pin indicating which external communication device is selected. The second connector also has common EMI and EMP protective filter circuits incorporated therein to protect the I/O interface subsystem.