Robert S Nuckolls from Fremont, CA, age 65

Name / Title

Company / Classification

Phones & Addresses

Robert Nuckolls
President

Funkyflick, Inc

3178 Atherton Dr, Santa Clara, CA 95051

Resumes

Senior Engineer At Google

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Location:

San Francisco Bay Area

Industry:

Computer Hardware

Senior Engineer At Sunw

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Location:

San Francisco Bay Area

Industry:

Computer Hardware

Us Patents

Register Window Fill Technique For Retirement Window Having Entry Size Less Than Amount Of Fill Instructions
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US Patent:

7035999, Apr 25, 2006
Filed:

Jun 7, 2002
Appl. No.:

10/165256
Inventors:

Sorin Iacobovici - San Jose CA, US
Rabin Sugumar - Sunnyvale CA, US
Robert Nuckolls - Santa Clara CA, US
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

G06F 9/22
US Classification:

712218, 712228, 712243
Abstract:

A register window fill technique for a retirement window having an entry size less than a number of fill instructions used in a fill condition is provided. The technique uses modified fill instructions that allow the retirement window to retire a portion of the fill instructions without having to determine whether a remaining portion of the fill instructions will execute without exceptions.

Register Window Flattening Logic For Dependency Checking Among Instructions
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US Patent:

7080237, Jul 18, 2006
Filed:

May 24, 2002
Appl. No.:

10/155391
Inventors:

Chandra M. R. Thimmannagari - Fremont CA, US
Sorin Iacobovici - San Jose CA, US
Rabin A. Sugumar - Sunnyvale CA, US
Robert Nuckolls - Santa Clara CA, US
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

G06F 9/30
US Classification:

712220, 712216
Abstract:

A technique for flattening architectural register windows into flattened space depending on a current window pointer to a register window is provided. The technique involves converting an n-bit value of a particular register in a register window to an x-bit value dependent on the current window pointer, where x is greater than n, and where the x-bit value is used for register dependency checking among a plurality of instructions.

Method And A System For Using Same Set Of Registers To Handle Both Single And Double Precision Floating Point Instructions In An Instruction Stream
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US Patent:

7191316, Mar 13, 2007
Filed:

Jan 29, 2003
Appl. No.:

10/353662
Inventors:

Rabin A. Sugumar - Sunnyvale CA, US
Sorin Iacobovici - San Jose CA, US
Robert Nuckolls - Sunnyvale CA, US
Chandra M. R. Thimmannagari - Fremont CA, US
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

G06F 9/30
G06F 9/40
G06F 15/00
US Classification:

712222, 712221
Abstract:

A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions that both index a same set of registers is provided. The system comprises a decode unit arranged to decode, stall, and forward at least one of the plurality of single precision and at least one of the plurality of double precision floating point instructions in a fetch group. The decode unit includes a first counter arranged to increment for each of the plurality of single precision floating point instructions forwarded down a pipeline; a second counter arranged to increment for each of the plurality of double precision floating point instructions forwarded down the pipeline; a first mask register and a second mask register. The first mask register is updated by each of the single precision floating point instructions forwarded and the second mask register is updated by each of the double precision floating point instructions forwarded.

Branch Prediction Structure With Branch Direction Entries That Share Branch Prediction Qualifier Entries
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US Patent:

7380110, May 27, 2008
Filed:

Sep 11, 2003
Appl. No.:

10/660169
Inventors:

Robert D. Nuckolls - Santa Clara CA, US
Rabin A. Sugumar - Sunnyvale CA, US
Chandra M. R. Thimmannagari - Fremont CA, US
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

G06F 9/40
G06F 9/44
US Classification:

712239, 712240
Abstract:

An efficient branch prediction structure is described that bifurcates a branch prediction structure into at least two portions where information stored in the second portion is aliased amongst multiple entries of the first portion. In this way, overall storage (and layout area) can be reduced and scaling with a branch prediction structure that includes a (2N)K×1 branch direction entries and a (N/2)K×1 branch prediction qualifier entries is less dramatic than conventional techniques. An efficient branch prediction structure includes entries for branch direction indications and entries for branch prediction qualifier indications. The branch direction indication entries are more numerous than the branch prediction qualifier entries. An entry from the branch direction entries is selected based at least in part on a corresponding instruction instance identifier and an entry from the branch prediction qualifier entries is selected based at least in part on least significant bits of the instruction instance identifier.

Register Window Spill Technique For Retirement Window Having Entry Size Less Than Amount Of Spill Instructions
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US Patent:

20030229771, Dec 11, 2003
Filed:

Jun 7, 2002
Appl. No.:

10/165268
Inventors:

Sorin Iacobovici - San Jose CA, US
Rabin Sugumar - Sunnyvale CA, US
Robert Nuckolls - Santa Clara CA, US
International Classification:

G06F009/30
US Classification:

712/218000, 712/228000
Abstract:

A register window spill technique for an retirement window having an entry size less than a number of spill instructions used in a spill condition is provided. The technique uses modified spill instructions that allow the retirement window to retire a portion of the spill instructions without having to determine whether a remaining portion of the spill instructions will execute without exceptions.

Method And System For Early Speculative Store-Load Bypass
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US Patent:

20040044881, Mar 4, 2004
Filed:

Aug 28, 2002
Appl. No.:

10/229495
Inventors:

Robert Maier - San Jose CA, US
Sorin Iacobovici - San Jose CA, US
Rabin Sugumar - Sunnyvale CA, US
Robert Nuckolls - Santa Clara CA, US
Ali Vahidsafa - Palo Alto CA, US
Chandra Thimmannagari - Fremont CA, US
Assignee:

Sun Microsystems, Inc.
International Classification:

G06F009/30
US Classification:

712/218000, 712/225000
Abstract:

In an embodiment, the present invention describes a method and apparatus for detecting RAW condition earlier in an instruction pipeline. The store instructions are stored in a special store bypass buffer (SBB) within an instruction decode unit (IDU). The IDU compares the instruction fields that are used for address generation of all ‘load’ instructions against ‘store’ instructions within a group of fetched instructions and ‘store’ instructions previously stored in the SBB. If a match of instruction fields is found, the IDU ‘speculates’ that the load instruction has dependency on the ‘store’ instruction. A data cache unit (DCU) validates the dependency of the load instruction ‘speculated’ by the IDU. If a false dependency is ‘speculated’ by the IDU, the DCU forces a re-fetch of the load instruction.

Scheme To Simplify Instruction Buffer Logic Supporting Multiple Strands
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US Patent:

20040128476, Jul 1, 2004
Filed:

Dec 26, 2002
Appl. No.:

10/329856
Inventors:

Robert Nuckolls - Santa Clara CA, US
Sorin Iacobovici - San Jose CA, US
Rabin Sugumar - Sunnyvale CA, US
Chandra Thimmannagari - Fremont CA, US
International Classification:

G06F009/30
US Classification:

712/206000, 712/215000
Abstract:

A method and apparatus for processing instructions involves an instruction fetch unit arranged to receive a plurality of instructions. The instruction fetch unit includes a bypass buffer arranged to receive at least a portion of a plurality of instructions, and an output multiplexer arranged to receive the at least a portion of the plurality of instructions where the output multiplexer is arranged to output an instruction selected from one of an output of the bypass buffer and the at least a portion of the plurality of instructions.

Strand Switching Algorithm To Avoid Strand Starvation
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US Patent:

20040128488, Jul 1, 2004
Filed:

Dec 26, 2002
Appl. No.:

10/329855
Inventors:

Chandra Thimmannagari - Fremont CA, US
Rabin Sugumar - Sunnyvale CA, US
Sorin Iacobovici - San Jose CA, US
Robert Nuckolls - Santa Clara CA, US
International Classification:

G06F009/00
US Classification:

712/235000
Abstract:

A method and apparatus for avoiding strand starvation is provided. The method and apparatus selectively switches from a first strand to a second strand dependent on a state of a computer system. The selectively switching is dependent on whether the second strand is alive and whether a value of a counter has reached a particular count.