Barry J Oldfield - Boise ID Robert A. Rust - Boise ID
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1200
US Classification:
711114, 711112, 714 6, 714 52, 714770, 714784
Abstract:
A disk controller includes memory that is accessible by both a microprocessor and hardware parity logic. Parity-related operations are identified by scenario, and parity coefficient subsets are stored in a memory table for each different parity-related calculation scenario. To perform a particular parity-related operation, the microprocessor determines the operations scenario and identifies the corresponding coefficient subset. The hardware parity logic is then instructed to perform the appropriate parity computation, using the identified coefficient subset. Parity segments are calculated by a parity segment calculation module that is embodied as an application specific integrated circuit (ASIC). The ASIC includes one or more local result buffers for holding intermediate computation results, one or more mathematical operator components configured to receive data strips, which are portions of larger data stripes, coefficients associated with the data strips, and operates on them to provide intermediate computation results that can be written to the local result buffers Upon completing the parity processing of a strip, the results are then stored in an external memory (e. g. , RAM). Upon completing the processing of all of the strips in a stripe, the final parity results are written to applicable sections of a stripe-based disk array.
Compression Algorithm With Embedded Meta-Data For Partial Record Operation Augmented With Expansion Joints
Robert A. Rust - Boise ID Douglas L. Voigt - Boise ID
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G11B 500
US Classification:
360 8, 360 48, 711111, 711114, 710 68, 707101
Abstract:
A compression system stores meta-data in the compressed record to allow better access and manage merging data. Markers are added to the compression stream to indicate various things. Each compressed record has a marker to indicate the start of the compressed data. These markers have sector number as well as the relocation block numbers embedded in their data. A second marker is used to indicate free space. When compressed data is stored on the disk drive, free space is reserved so that future compression of the same, or modified, data has the ability to expand slightly without causing the data to be written to a different location. Also the compressed data can shrink and the remaining space can be filled in with this free space marker. A third type of marker is the format pattern marker. Compression algorithms generally compress the format pattern very tightly.
Redundant Data Storage Systems And Methods Of Operating A Redundant Data Storage System
Robert A. Rust - Boise ID Barry J Oldfield - Boise ID Christopher W Johansson - Horseshoe Bend ID Christine Grund - Meridian ID
Assignee:
Hewlett Packard Development Company, L. P. - Houston TX
International Classification:
G06F 1200
US Classification:
711114, 710 39, 710 40, 711158, 711162, 714 6
Abstract:
Redundant data storage systems and methods of operating a redundant data storage system are presented. In one aspect of the invention, a redundant data storage system includes: a plurality of storage devices configured to redundantly store digital data; a plurality of transaction originating devices configured to originate a plurality of transactions to control operations of the storage devices; a plurality of parallel data buses configured to communicate data relative to the respective transaction originating devices; and a plurality of transaction processing devices coupled with the parallel data buses and configured to process the transactions in an order according to a transaction ordering protocol common to at least some of the transaction processing devices.
Robert A. Rust - Boise ID Barry J Oldfield - Boise ID
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1100
US Classification:
714811, 714799
Abstract:
Methods and systems for fault location are described. In one described embodiment, an âin circuitâ solution is provided for locating faults along a passive transmission line. Once a fault occurs, various hardware gathers information that is necessary to determine which of a number of different replaceable components has failed. This enables the subsystem to properly respond to the fault condition and thereby eliminate any guessing that could potentially lead to loss of data availability. In the particular described embodiment, signals are driven and received through a selected input/output (I/O) pad. Logic circuitry is provided and launches a wave onto the passive transmission line. Immediately following the launching of the wave, the I/O pad is monitored and can sense the reflections from the wave that has just been launched. By analyzing the reflections, and more specifically the time that it takes for the reflection to be sensed, a determination is made as to the fault location.
Fault Tolerant Data Storage Systems And Methods Of Operating A Fault Tolerant Data Storage System
Robert A. Rust - Boise ID Barry J. Oldfield - Boise ID Steven Lee Shrader - Boise ID Christine Grund - Meridian ID Christopher W. Johansson - Horseshoe Bend ID
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1100
US Classification:
714 48, 714 6, 714 52
Abstract:
Fault tolerant data storage systems and methods of operating a fault tolerant data storage system are presented. In one aspect of the invention, a fault tolerant data storage system comprises: a plurality of coupled components individually including: an interface adapted to couple with a data connection and to selectively receive a plurality of transactions from the data connection; transaction processing circuitry coupled with the interface and configured to process transactions received from the interface; and analysis circuitry configured to detect error conditions within the transactions and to prevent entry of transactions individually including an error condition into the respective component responsive to the detection.
Methods And Apparatus For Verifying The Installation Of Components In A System
A verification system for an interchangeable component configured to be mated with a receiving system. The system includes a key device supported by the interchangeable component. The key device includes a transmitter configured to transmit a signal comprising component identification characteristics. The system further includes a lock system having a signal receiver and a verification component. The signal receiver is configured to receive the signal from the key device transmitter and pass the signal to the verification component. The verification component is configured to use the signal to determine whether or not the component should be admitted to the receiving system, and to generate an authorization signal if the component should be admitted.
Methods And Systems Of Using Result Buffers In Parity Operations
Barry J Oldfield - Boise ID Robert A. Rust - Boise ID
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1100
US Classification:
714801, 714770, 714781
Abstract:
A disk controller includes memory that is accessible by both a microprocessor and hardware parity logic. Parity-related operations are identified by scenario, and parity coefficient subsets are stored in a memory table for each different parity-related calculation scenario. To perform a particular parity-related operation, the microprocessor determines the operations scenario and identifies the corresponding coefficient subset. The hardware parity logic is then instructed to perform the appropriate parity computation, using the identified coefficient subset. In one embodiment, parity segments are calculated by a parity segment calculation module that is embodied as an application specific integrated circuit (ASIC). The ASIC includes one or more result buffers for holding intermediate computation results, one or more mathematical operator components configured to receive data segments and coefficients associated with the data segments and operate on them to provide intermediate computation results that can be written to the one or more result buffers, and one or more feedback lines. The feedback lines are coupled between an associated result buffer and an associated mathematical operator component and provide an intermediate computation result to the math operator for use in calculating parity segments.
Using Task Description Blocks To Maintain Information Regarding Operations
Barry J Oldfield - Boise ID Robert A. Rust - Boise ID
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1100
US Classification:
714 52
Abstract:
A disk controller includes memory that is accessible by both a microprocessor and an operation logic. Information needed by the operation logic to perform an operation is stored in a task description block in memory by the microprocessor, and a pointer to the task description block is added to a task description block queue. The operation logic is then able to access task description blocks, based on the pointers in the queue, at will and perform the corresponding operations.
Worldwide Travel Staffing, Ltd.
Gc
Onondaga County District Attorney's Office 2007 - 2009
Assistant District Attorney
Skadden, Arps, Slate, Meagher & Flom Llp and Affiliates 2005 - 2007
Litigation Support
Education:
Elisabeth Haub School of Law at Pace University 2004 - 2007
Doctor of Jurisprudence, Doctorates, Law
Syracuse University 2001 - 2002
Master of Science, Masters, Telecommunications, Management
Syracuse University 1998 - 2001
Bachelors, Bachelor of Science, Information Systems
Le Moyne College
Skills:
Litigation Civil Litigation Legal Research Legal Writing Commercial Litigation Intellectual Property Criminal Law Courts Licensing Criminal Justice Legal Issues Westlaw
Production Designer, Sound Technician, Wed Designer, Visual ConsultantAgua Fri Hardware
Sales AssociateMBK Studios
TeacherHappy Days Entertainment
DriverGeneral Labor
Bud Murphy's- Dish WasherLake Arrowhead Yacht Club
Busser/ DishEl Caballero Country Club
Cart/ Driving Range/ Bag attendant
Education:
California State University Northridge 2011 to 2013 BA in Multimedia ProductionVictor Valley College/ Pierce College 2007 to 2010 AA in Arts and Humanities
Dr. Rust graduated from the University of Virginia School of Medicine in 1981. He works in Charlottesville, VA and specializes in Child Neurology and Neurology. Dr. Rust is affiliated with University Of Virginia Medical Center.
Cycles Of Life Healthcare 1301 N Division Ave, Sandpoint, ID 83864 2082631345 (phone), 2082555531 (fax)
Education:
Medical School Creighton University School of Medicine Graduated: 1967
Languages:
English
Description:
Dr. Rust graduated from the Creighton University School of Medicine in 1967. He works in Sandpoint, ID and specializes in General Practice and Addiction Medicine.
Medical School University of North Dakota College of Medicine Graduated: 1979
Languages:
English
Description:
Dr. Rust graduated from the University of North Dakota College of Medicine in 1979. He works in Mishawaka, IN and specializes in Diagnostic Radiology. Dr. Rust is affiliated with Community Hospital Of Bremen and Saint Joseph Regional Medical Center.
4461 Kohler Drive, Allentown, PA 18103-6029Owning Member at Rust & Associates Law Firm LLC A native of Vriginia, my wife, Lee Anne, and I raised our children in Lower Macungie Township, all three of whom went throughthe East Penn School system. For a... A native of Vriginia, my wife, Lee Anne, and I raised our children in Lower Macungie Township, all three of whom went throughthe East Penn School system. For a number of years I was a principal in financial and estate planning firm with a national clientele. After leaving this firm, I was involved...
Highland Elementary School Tonawanda NY 1960-1964, Broadmor Elementary School Tempe AZ 1964-1965, Rowland Hall-St. Mark's High School Salt Lake City UT 1968-1969