Robert L Totorica

US Patent:

6433570, Aug 13, 2002

Filed:

Oct 31, 2000

Appl. No.:

09/703354

Inventors:

Michael J. Sharpes - Boise ID
Robert L. Totorica - Boise ID

Assignee:

Micron Technology Inc. - Boise ID

International Classification:

G01R 3100

US Classification:

324760, 324765

Abstract:

A compact and modularly designed apparatus for testing and burning-in semiconductor devices comprises first and second power supplies and the use of direct current (DC) to DC converters. The first power supply provides a high voltage low amperage power source to drive the devices under test (DUTs), and the second power supply supplies 15 volts and 5 volts to drive the circuitry on the testing equipment. The high voltage and low amperage is supplied to slot boards, and the DC to DC converters alter the voltage and current to digital levels. Supplying high voltage and low amperage power through the system to a location electrically near the DUTs, then converting it with DC to DC converters to power the DUTs, allows for much smaller connectors and for a modularly designed burn-in oven.

US Patent:

6441606, Aug 27, 2002

Filed:

Oct 17, 2000

Appl. No.:

09/690564

Inventors:

John Caldwell - Meridian ID
James Nuxoll - Boise ID
Robert Totorica - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 3102

US Classification:

3241581, 324760, 324765

Abstract:

A wafer cassette includes a stationary dual-zone temperature control base and a removable wafer cassette top. The top includes a main cassette support structure, onto which wafer test electronics, a test interface connector, a wafer interconnect assembly, a wafer test area, a flex film interconnect, and a wafer chuck with evacuation chamber and electric wafer heater, and at least one rough alignment fixture are mounted. A wafer to be tested is inserted, with a pressure-isolating seal, between the wafer chuck and the wafer test area. The base is a stationary fixed portion which includes a first support compartment, a second support compartment and thermal circuits, each of which includes fluid inlet and outlet connections. The fixed portion further includes a heater interconnect to provide connection and external access for a heater element, as well as a vacuum interconnect line to provide external connection to the evacuation chamber. The first and second support compartments are adjacently spaced, and each contains at least one of each of the thermal circuits.

US Patent:

6581172, Jun 17, 2003

Filed:

Jan 16, 2001

Appl. No.:

09/764568

Inventors:

Robert L. Totorica - Boise ID
Charles K. Snodgrass - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 2900

US Classification:

714718, 714 30, 714724, 714733, 714734, 3241581

Abstract:

A system allowing testing a plurality of integrated circuits mounted on a common substrate is described. The testing system includes a failure processor mounted on the substrate. The substrate has a first signal port adapted to be coupled to a testing device. The failure processor has a second signal port coupled to the first signal port and a plurality of test ports corresponding in number to the number of integrated circuits mounted on the substrate that are to be tested. Each of the test ports may be coupled to a respective one of the integrated circuits. The failure processor is constructed to apply stimulus signals to each of the integrated circuits and to record response signals generated by each of the integrated circuits in response to the stimulus signals provided to the integrated circuits. The failure processor is further constructed to provide report data based on the response signals and to couple the report data from the second signal port to the first signal port. As a result, many integrated circuits under test may share the first signal port through the failure processor, because the integrated circuits under test are not providing output data on the first signal port to an external test data evaluation apparatus.

US Patent:

6799289, Sep 28, 2004

Filed:

Feb 10, 2003

Appl. No.:

10/364745

Inventors:

Robert L. Totorica - Boise ID
Charles K. Snodgrass - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 2900

US Classification:

714718, 714724, 714733, 714 30, 3241581

Abstract:

A system allowing testing a plurality of integrated circuits mounted on a common substrate is described. The testing system includes a failure processor mounted on the substrate. The substrate has a first signal port adapted to be coupled to a testing device. The failure processor has a second signal port coupled to the first signal port and a plurality of test ports corresponding in number to the number of integrated circuits mounted on the substrate that are to be tested. Each of the test ports may be coupled to a respective one of the integrated circuits. The failure processor is constructed to apply stimulus signals to each of the integrated circuits and to record response signals generated by each of the integrated circuits in response to the stimulus signals provided to the integrated circuits. The failure processor is further constructed to provide report data based on the response signals and to couple the report data from the second signal port to the first signal port. As a result, many integrated circuits under test may share the first signal port through the failure processor, because the integrated circuits under test are not providing output data on the first signal port to an external test data evaluation apparatus.

US Patent:

7319340, Jan 15, 2008

Filed:

Aug 1, 2005

Appl. No.:

11/195514

Inventors:

Joseph M. Jeddeloh - Shoreview MN, US
Robert Totorica - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 31/02

US Classification:

324763, 3241581

Abstract:

An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit generates test signals that are applied to the integrated circuit sockets. The integrated test circuit also receives response signals from the integrated circuit sockets indicative of the manner in which integrated circuits in the sockets responded to the test signals. Several of the load boards may be placed on a test head that may be coupled to a host.

US Patent:

7328381, Feb 5, 2008

Filed:

Aug 1, 2005

Appl. No.:

11/195035

Inventors:

Joseph M. Jeddeloh - Shoreview MN, US
Robert Totorica - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 29/00
H03M 13/00

US Classification:

714718, 714758, 714 42

Abstract:

A testing method and system is used to test memory modules each of which has a memory hub coupled to a plurality of memory devices. The testing system and method includes a test interface circuit having a memory interface that is coupled to transmit and receive memory signals to and from a tester through a memory bus. The test interface circuit couples test signals to the memory hub in the memory module through a communications link responsive to command, address and data signals received from the tester. The test interface circuit also receives signals from the memory hub in the memory module through the communications link that are indicative of the response of the memory module to the test signals. The test interface circuit then provides corresponding results data to the tester.

US Patent:

7521948, Apr 21, 2009

Filed:

Apr 6, 2007

Appl. No.:

11/784346

Inventors:

Joseph M. Jeddeloh - Shoreview MN, US
Robert Totorica - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 31/02

US Classification:

324754, 324765

Abstract:

An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit generates test signals that are applied to the integrated circuit sockets. The integrated test circuit also receives response signals from the integrated circuit sockets indicative of the manner in which integrated circuits in the sockets responded to the test signals. Several of the load boards may be placed on a test head that may be coupled to a host. The integrated test circuit may also be used with an integrated circuit probe card, where the test signals are applied to an integrated circuit coupled to the probe card.

US Patent:

61924954, Feb 20, 2001

Filed:

Jul 10, 1998

Appl. No.:

9/113940

Inventors:

Robert L. Totorica - Boise ID
Charles K. Snodgrass - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 2900
G01R 3128

US Classification:

714718

Abstract:

A system allowing testing a plurality of integrated circuits mounted on a common substrate is described. The testing system includes a failure processor mounted on the substrate. The substrate has a first signal port adapted to be coupled to a testing device. The failure processor has a second signal port coupled to the first signal port and a plurality of test ports corresponding in number to the number of integrated circuits mounted on the substrate that are to be tested. Each of the test ports may be coupled to a respective one of the integrated circuits. The failure processor is constructed to apply stimulus signals to each of the integrated circuits and to record response signals generated by each of the integrated circuits in response to the stimulus signals provided to the integrated circuits. The failure processor is further constructed to provide report data based on the response signals and to couple the report data from the second signal port to the first signal port. As a result, many integrated circuits under test may share the first signal port through the failure processor, because the integrated circuits under test are not providing output data on the first signal port to an external test data evaluation apparatus.