Rodney A Browen

US Patent:

6467051, Oct 15, 2002

Filed:

Oct 9, 1998

Appl. No.:

09/169421

Inventors:

Rodney A. Browen - Loveland CO
Cherif Ahrikencheikh - Loveland CO
William P. Darbie - Longmont CO
John E. McDermid - Loveland CO
Kay C. Lannen - Ft. Collins CO

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

G06F 1338

US Classification:

714 30, 714724, 714738, 709183

Abstract:

A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.

US Patent:

62634763, Jul 17, 2001

Filed:

Oct 9, 1998

Appl. No.:

9/169777

Inventors:

Rodney A. Browen - Loveland CO
Cherif Ahrikencheikh - Loveland CO
William P. Darbie - Longmont CO
John E. McDermid - Loveland CO
Kay C. Lannen - Ft. Collins CO

Assignee:

Agilent Technologies - Palo Alto CA

International Classification:

G06F 1750
G06F 1125

US Classification:

716 4

Abstract:

A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.

US Patent:

46528148, Mar 24, 1987

Filed:

Jun 13, 1983

Appl. No.:

6/503464

Inventors:

William A. Groves - Loveland CO
Matthew L. Snook - Loveland CO
Rodney Browen - Loveland CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G01R 3128

US Classification:

324 73R

Abstract:

A circuit tester and test technique are presented that compresses the amount of data stored in local test data RAMs for the implementation of a circuit test, thereby reducing the amount of data that must be downloaded to the local test data RAMs, thereby improving test throughput. Derivative data vectors are utilized in addition to raw data vectors as part of the data compression technique. Further compression results from storing only unique data vectors in the local test data RAMs and utilizing a sequencer to control the order in which the unique data vectors are utilized. The sequencer includes test program logic and logic capable of implementing on test pins indirect counters.

US Patent:

62667874, Jul 24, 2001

Filed:

Oct 9, 1998

Appl. No.:

9/169597

Inventors:

John E. McDermid - Loveland CO
Cherif Ahrikencheikh - Loveland CO
Rodney A. Browen - Loveland CO
William P. Darbie - Longmont CO
Kay C. Lannen - Ft. Collins CO

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

G05B 19048

US Classification:

714 33

Abstract:

A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.

US Patent:

62371185, May 22, 2001

Filed:

Oct 9, 1998

Appl. No.:

9/169709

Inventors:

Cherif Ahrikencheikh - Loveland CO
Rodney A. Browen - Loveland CO
William P. Darbie - Longmont CO
John E. McDermid - Loveland CO

Assignee:

Agilent Technologies - Palo Alto CA

International Classification:

G01R 3128

US Classification:

714724

Abstract:

A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.

US Patent:

63275457, Dec 4, 2001

Filed:

Oct 9, 1998

Appl. No.:

9/169710

Inventors:

Rodney A. Browen - Loveland CO
Cherif Ahrikencheikh - Loveland CO
William P. Darbie - Longmont CO
John E. McDermid - Loveland CO

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

G01R 3500

US Classification:

702 85

Abstract:

A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.

US Patent:

46425616, Feb 10, 1987

Filed:

Jan 3, 1984

Appl. No.:

6/567824

Inventors:

William A. Groves - Loveland CO
Matthew L. Snook - Loveland CO
Rodney Browen - Loveland CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G01R 3128

US Classification:

324 73R

Abstract:

A circuit tester and test technique are presented that compresses the amount of data stored in local test data RAMs for the implementation of a circuit test, thereby reducing the amount of data that must be downloaded to the local test data RAMs, thereby improving test throughput. Derivative data vectors are utilized in addition to raw data vectors as part of the data compression technique. Further compression results from storing only unique data vectors in the local test data RAMs and utilizing a sequencer to control the order in which the unique data vectors are utilized. The sequencer includes test program logic and logic capable of implementing on test pins indirect counters.

US Patent:

62337068, May 15, 2001

Filed:

Oct 9, 1998

Appl. No.:

9/169320

Inventors:

Cherif Ahrikencheikh - Loveland CO
Rodney A. Browen - Loveland CO
William P. Darbie - Longmont CO
John E. McDermid - Loveland CO

Assignee:

Agilent Technologies - Palo Alto CA

International Classification:

G01R 3128

US Classification:

714724

Abstract:

A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.