Rodney M Phelps

US Patent:

6954908, Oct 11, 2005

Filed:

Dec 10, 2002

Appl. No.:

10/315437

Inventors:

Pero Subasic - Pittsburgh PA, US
Rodney Phelps - Pittsburgh PA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F017/50

US Classification:

716 1, 716 8, 716 9

Abstract:

A visualization and data mining technique can be utilized to facilitate analysis of generated sets of design points for an integrated circuit to enable easy and fast understanding of important properties of generated designs. The use of the visualization and data mining technique significantly reduces the time needed for analysis of design space and decision on which design point to choose for implementing into a circuit design.

US Patent:

6957400, Oct 18, 2005

Filed:

Aug 29, 2003

Appl. No.:

10/652018

Inventors:

Hongzhou Liu - Pittsburgh PA, US
Rodney Phelps - Pittsburgh PA, US
Rob A. Rutenbar - Pittsburgh PA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F017/50

US Classification:

716 1, 716 2, 716 18

Abstract:

To identify high quality design points in a circuit design, a plurality of design points is generated for the circuit. A subset of the design points is allocated to a design population. A cost is then determined for each allocated design point. From a subset of the allocated design points, a plurality of new design points is generated for the circuit. The cost for each new design point is then determined and each new design point having a cost that is the same or more favorable than the most favorable cost associated with the allocated design points is allocated to the design population. The design points allocated to the design population can then be displayed for selection of one of said allocated design points having desired performances of the circuit.

US Patent:

7003745, Feb 21, 2006

Filed:

Aug 11, 2003

Appl. No.:

10/638625

Inventors:

Pero Subasic - Pittsburgh PA, US
Rodney Phelps - Pittsburgh PA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50
G06F 10/13

US Classification:

716 4, 716 18, 703 2, 703 14, 703 15, 703 16, 703 21

Abstract:

Each circuit simulation performed on unique layout of circuit devices generates a design point (DP) that includes device variable values and performance goal values. Circuit models for at least one performance goal are determined as a function of a first subset of the DPs. A performance goal value is determined for each circuit model based on the device variable values obtained from a second subset of the DPs. Errors are determined between the thus determined value of each performance goal and values of the corresponding performance goals obtained from the second subset of the DPs. Input values of device variables are processed with at least one of the circuit models having the smallest error associated therewith to determine therefor a performance goal value. A layout of the circuit devices is generated based on the input device variable values associated with at least one of the thus determined performance goals.

US Patent:

7058916, Jun 6, 2006

Filed:

Jun 18, 2002

Appl. No.:

10/174395

Inventors:

Rodney Phelps - Pittsburgh PA, US
Ronald A. Rohrer - Saratoga CA, US
Anthony J. Gadient - Pittsburgh PA, US
Rob A. Rutenbar - Pittsburgh PA, US
L. Richard Carley - Sewickley PA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 11, 716 1, 716 2, 716 4, 716 7, 716 8, 716 16, 716 17

Abstract:

In a method of automatically sizing and biasing a circuit, a database is provided including a plurality of records related to cells that can be utilized to form an integrated circuit. A cell parameter of a cell for a circuit is selected and compared to cell parameters residing in the records stored in the database. One record in the database is selected based upon this comparison and a performance characteristic of the circuit is determined from this record.

US Patent:

7346868, Mar 18, 2008

Filed:

Mar 11, 2005

Appl. No.:

11/078573

Inventors:

Rodney M. Phelps - Pittsburgh PA, US
Hongzhou Liu - Pittsburgh PA, US
Amith Singhee - Pittsburgh PA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 7

Abstract:

Method and system for evaluating design costs of an integrated circuit are disclosed. The method includes choosing a design point for evaluation, dividing circuit specifications of the design point into at least two groups comprising a first group of specifications and a second group of specifications, computing a first set of design costs for the first group of specifications, estimating a second set of design costs for the second group of specifications using a predetermined set of reference costs, and determining a design cost of the design point using the first set of design costs and the second set of design costs.

US Patent:

7493574, Feb 17, 2009

Filed:

Feb 23, 2006

Appl. No.:

11/361928

Inventors:

Hongzhou Liu - Pittsburgh PA, US
Rodney M. Phelps - Pittsburgh PA, US

Assignee:

Cadence Designs Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 1, 716 2, 716 4

Abstract:

Method and system for improving yield of an integrated circuit are disclosed. The method includes optimizing a design of the integrated circuit according to a set of predefined design parameters to generating design points that meet a set of predefined design specifications, analyzing the design points to form clusters comprising the design points, determining a representative design point from the clusters comprising the design points, running a statistical simulation to determine a yield of the design using the representative design point and a statistical model of manufacturing process variations, generating statistical corners in accordance with results of the statistical simulation, and optimizing the design in accordance with the statistical corners using an iterative process.

US Patent:

8255849, Aug 28, 2012

Filed:

Apr 14, 2009

Appl. No.:

12/423722

Inventors:

Vladimir Okhmatovski - Winnipeg, CA
Mengtao Yuan - Santa Clara CA, US
Rodney Phelps - Pittsburgh PA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716110

Abstract:

Systems and methods for modeling a multilayer integrated circuit include three-dimensional interconnect models in multilayered substrates for greater accuracy. Mesh models are used to resolve effects of nearby elements and grid models are used to resolve effects of far-away elements. Sidewall mesh elements of three-dimensional interconnects are projected onto parallel (or substantially parallel) grids between the top and bottom walls of the interconnects so that grid models can be used to resolve three-dimensional effects of interconnects in multilayered substrates.

US Patent:

8312402, Nov 13, 2012

Filed:

Apr 14, 2009

Appl. No.:

12/423714

Inventors:

Vladimir Okhmatovski - Winnipeg, CA
Mengtao Yuan - Santa Clara CA, US
Rodney Phelps - Pittsburgh PA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 9/455
G06F 17/50

US Classification:

716113, 716120, 716137

Abstract:

Systems and methods for modeling a multilayer integrated circuit include three-dimensional interconnect models in multilayered substrates for greater accuracy. Mesh models are used to resolve effects of nearby elements and grid models are used to resolve effects of far-away elements. Sidewall mesh elements of three-dimensional interconnects are projected onto parallel (or substantially parallel) grids between the top and bottom walls of the interconnects so that grid models can be used to resolve three-dimensional effects of interconnects in multilayered substrates.