Rodolfo G Beraha

US Patent:

6697276, Feb 24, 2004

Filed:

Feb 1, 2002

Appl. No.:

10/062307

Inventors:

Jose P. Pereira - Cupertino CA
Sunder R. Rathnavelu - Marlboro NJ
Rodolfo G. Beraha - Redwood City CA
Lewis M. Carroll - Plano TX
Ronald S. Jankov - Woodside CA

Assignee:

NetLogic Microsystems, Inc. - Mountain View CA

International Classification:

G11C 1500

US Classification:

365 49, 36518907, 711108

Abstract:

A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives the index from the index generator and outputs a stored data value from a location indicated by the index. A compare circuit receives the data value from the memory and compares the data value and the search value to generate a match signal indicative of whether the data value and search value match. The match signal and index are output from the CAM device.

US Patent:

6934796, Aug 23, 2005

Filed:

Feb 1, 2002

Appl. No.:

10/061941

Inventors:

Jose P. Pereira - Cupertino CA, US
Sunder R. Rathnavelu - Marlboro NJ, US
Rodolfo G. Beraha - Redwood City CA, US
Lewis M. Carroll - Plano TX, US
Ronald S. Jankov - Woodside CA, US

Assignee:

NetLogic Microsystems, Inc. - Mountain View CA

International Classification:

G06F012/00

US Classification:

711108, 365 49

Abstract:

A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives the index from the index generator and outputs a stored data value from a location indicated by the index. A compare circuit receives the data value from the memory and compares the data value and the search value to generate a match signal indicative of whether the data value and search value match. The match signal and index are output from the CAM device.

US Patent:

7193874, Mar 20, 2007

Filed:

Nov 22, 2003

Appl. No.:

10/719099

Inventors:

Jose P. Pereira - Cupertino CA, US
Sunder R. Rathnavelu - Marlboro NJ, US
Rodolfo G. Beraha - Redwood City CA, US
Lewis M. Carroll - Plano TX, US
Ronald S. Jankov - Woodside CA, US

Assignee:

Netlogic Microsystems, Inc. - Mountain View CA

International Classification:

G11C 15/00
G11C 7/00

US Classification:

365 49, 36518907, 36518902

Abstract:

A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives the index from the index generator and outputs a stored data value from a location indicated by the index. A compare circuit receives the data value from the memory and compares the data value and the search value to generate a match signal indicative of whether the data value and search value match. The match signal and index are output from the CAM device.

US Patent:

20140043962, Feb 13, 2014

Filed:

Aug 7, 2012

Appl. No.:

13/568810

Inventors:

Venkat Rangan - San Diego CA, US
Jeffrey A. Levin - San Diego CA, US
Rodolfo G. Beraha - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H04L 12/26

US Classification:

370228, 370410, 370252

Abstract:

Certain aspects of the present disclosure support techniques for collecting system information in a network on a chip (NoC). A dedicated packet may be transmitted from a source node to a destination node. As it traverses through the NoC, the dedicated packet may collect information from various nodes, which may be made available by the destination node. The collected information may be used in an effort to detect failures and collect statistics regarding the NoC.

US Patent:

57544581, May 19, 1998

Filed:

May 30, 1996

Appl. No.:

8/655581

Inventors:

Rodolfo Beraha - Los Altos CA
Robert H. Miller - Loveland CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 738
G06F 700

US Classification:

36474803

Abstract:

A method and apparatus for determining the trailing bit position from a two operand addition is described. The determination of the trailing bit occurs in parallel with the addition. The two operands are encoded together and the encoded word used to determine the trailing bit position. As the operations of encoding the operands and operating upon the encoded operands require no more time than known methods to determine the trailing bit position after the addition is completed, and as the encoding and operating on the encoded words occurs in parallel with the addition operation, the present invention allows faster processing in the floating point unit.

US Patent:

20190251425, Aug 15, 2019

Filed:

Feb 15, 2019

Appl. No.:

16/277768

Inventors:

- La Jolla CA, US
Karim Arabi - San Diego CA, US
Rodolfo Beraha - San Diego CA, US

International Classification:

G06N 3/063
G06F 17/16
G06N 3/04

Abstract:

Disclosed are methods, apparatus and systems for a binary neural network accelerator engine. One example circuit is designed to perform a multiply-and-accumulate (MAC) operation using logic circuits that include a first set of exclusive nor (XNOR) gates to generate a product vector based on a bit-wise XNOR operation two vectors. The result is folded and operated on by another set of logic circuits that provide an output for a series of adder circuits. The MAC circuit can be implemented as part of binary neural network at a small footprint to effect power and cost savings.

US Patent:

20170160928, Jun 8, 2017

Filed:

Dec 2, 2015

Appl. No.:

14/956728

Inventors:

- San Diego CA, US
Amin Ansari - San Diego CA, US
Rodolfo Beraha - San Diego CA, US

International Classification:

G06F 3/06

Abstract:

Systems and methods are disclosed for a hybrid parallel-serial memory access by a system on chip (SoC). The SoC is electrically coupled to the memory by both a parallel access channel and a separate serial access channel. A request for access to the memory is received. In response to receiving the request to access the memory, a type of memory access is identified. A determination is then made whether to access the memory with the serial access channel. In response to the determination to access the memory with the serial access channel, a first portion of the memory is accessed with the parallel access channel, and a second portion of the memory is accessed with the serial access channel.

US Patent:

20170017576, Jan 19, 2017

Filed:

Jul 16, 2015

Appl. No.:

14/801329

Inventors:

- San Diego CA, US
Kishore Yalamanchili - San Diego CA, US
Amin Ansari - San Diego CA, US
Amrit Kumar Panda - San Diego CA, US
Rodolfo Giacomo Beraha - San Diego CA, US

International Classification:

G06F 12/08
G06N 5/04
G06N 99/00

Abstract:

Aspects include computing devices, systems, and methods for implementing generating a cache memory configuration. A server may apply machine learning to context data. The server may determine a cache memory configuration relating to the context data for a cache memory of a computing device and predict execution of an application on the computing device. Aspects include computing devices, systems, and methods for implementing configuring a cache memory of the computing device. The computing device may classify a plurality of cache memory configurations, related to a predicted application execution, based on at least a hardware data threshold and a first hardware data. The computing device may select a first cache memory configuration from the plurality of cache memory configurations in response to the first cache memory configuration being classified for the first hardware data, and configuring the cache memory at runtime based on the first cache memory configuration.