Ryan Lee Akkerman

US Patent:

7348799, Mar 25, 2008

Filed:

Jan 11, 2005

Appl. No.:

11/032949

Inventors:

John A. Benavides - Garland TX, US
Tyler J. Johnson - Murphy TX, US
Ryan Lee Akkerman - Allen TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 7/38
G06F 12/00
H03K 19/173

US Classification:

326 46, 711100, 712232

Abstract:

One disclosed embodiment may comprise an application specific integrated circuit (ASIC). The ASIC includes memory that stores condition data defining conditions for enabling transitions among a plurality of states and next state data defining a next state associated with each of the respective conditions. A state machine circuit employs the condition data and the next state data to transition from a current state of the state machine circuit to a next state as a function of applying at least one condition relative to input data. The at least one condition is defined by condition data that is associated with the current state. The state machine circuit associates next state data with the at least one condition based on the current state of the state machine circuit. A control circuit provides a trigger signal in response to the current state of the state machine circuit transitioning to at least one predefined state of the plurality of states.

US Patent:

7382847, Jun 3, 2008

Filed:

Jul 23, 2004

Appl. No.:

10/898404

Inventors:

Richard W. Adkisson - Dallas TX, US
Ryan L. Akkerman - Allen TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H04L 25/00
H04L 7/00

US Classification:

375371, 375354

Abstract:

A programmable sync pulse generator and sync pulse generation method are operable in a clock synchronizer to effectuate data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. The first clock domain is operable with a first clock signal and the second clock domain is operable with a second clock signal. A phase detection circuitry is operable to sample the first clock signal with the second clock signal to determine coincident edges of the first and second clock signals. Validation circuitry is operable to validate the coincident edges based upon skew tolerance between the first and second clock signals and to generate a valid edge signal responsive thereto. Sync generation circuitry, responsive to the valid edge signal, is operable to generate synchronization pulses in the first clock domain and synchronization pulses in the second clock domain.

US Patent:

7752016, Jul 6, 2010

Filed:

Jan 11, 2005

Appl. No.:

11/032743

Inventors:

Tyler J. Johnson - Murphy TX, US
Ryan Lee Akkerman - Allen TX, US
John A. Benavides - Garland TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/30

US Classification:

702186

Abstract:

A system includes a monitoring system that provides at least one signal as a function of at least some data provided on a bus. A measure of performance for the at least some data is adjusted based on the at least one signal. An analysis system is operative to perform logic analysis of the data on the bus as a function of the at least one signal.

US Patent:

7809991, Oct 5, 2010

Filed:

Jan 11, 2005

Appl. No.:

11/033226

Inventors:

Tyler J. Johnson - Murphy TX, US
Ryan Lee Akkerman - Allen TX, US
John A. Benavides - Garland TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 45, 714 47

Abstract:

One disclosed embodiment may comprise a system that includes a qualification system that qualifies data on an associated bus for capture and provides a qualification signal as a function of at least one signal that describes a characteristic of the data on the associated bus. A data capture system stores qualified data from the associated bus based on the qualification signal and a trigger signal, the trigger signal defining a capture session.

US Patent:

8019920, Sep 13, 2011

Filed:

Oct 1, 2008

Appl. No.:

12/243420

Inventors:

Ryan L. Akkerman - Allen TX, US
Harvey Ray - Frederick CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 3/00

US Classification:

710 52, 710 56

Abstract:

The system includes a microprocessor, a first buffer, a second buffer, and a control circuit. The control circuit includes a memory and an interface. The control circuit is configured to determine a first buffer value and compare the first buffer value to a predetermined value to obtain a result. The control circuit is further configured to control a read issue rate of the first buffer based on the result. The memory is configured to store at least one of the first buffer value, the result, the read issue rate, and the TAG.

US Patent:

20040193931, Sep 30, 2004

Filed:

Mar 26, 2003

Appl. No.:

10/397555

Inventors:

Ryan Akkerman - Allen TX, US
Richard Adkisson - Dallas TX, US

International Classification:

G06F001/12

US Classification:

713/400000

Abstract:

A system and method using a synchronizer circuit for effectuating data transfer across a clock domain boundary between a first clock domain and a second clock domain, wherein the first clock domain is operable with a first clock signal and the second clock domain is operable with a second clock signal. The first and second clock signals have a ratio of N first clock cycles to (N-) second clock cycles. A first circuit portion operates to transfer (N-) data bits, based on which clock cycle of the first clock signal has an extra data bit, out of N data bits across the clock boundary on a first data path of the synchronizer output. A second circuit portion operates to transfer the remaining extra data bit on a second data path of the synchronizer's output.

US Patent:

20040225977, Nov 11, 2004

Filed:

May 8, 2003

Appl. No.:

10/431823

Inventors:

Ryan Akkerman - Allen TX, US

International Classification:

G06F009/45
G06F017/50

US Classification:

716/006000

Abstract:

A system and method for simulating clock drift between asynchronous clock domains. In one embodiment, a first circuit portion is positioned in a first clock domain to transmit a first data sequence. An intermediate circuit portion receives the first data sequence and, responsive to a control signal, transmits a second data sequence to a second circuit portion positioned in a second clock domain. The second data sequence is subjected to drift relative to the first data sequence.

US Patent:

20050160328, Jul 21, 2005

Filed:

Jan 12, 2004

Appl. No.:

10/756530

Inventors:

Gregg Lesartre - Ft. Collins CO, US
David Hannum - Ft. Collins CO, US
Ryan Akkerman - Allen TX, US

International Classification:

G06F011/00

US Classification:

714048000

Abstract:

A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.