Sandeep Jaisingh Agarwal

US Patent:

6735349, May 11, 2004

Filed:

Sep 15, 1999

Appl. No.:

09/396299

Inventors:

Sandeep Agarwal - Fremont CA
Arun Johary - San Jose CA

Assignee:

Genesis Microchip Inc. - Alviso CA

International Classification:

G06K 932

US Classification:

382298, 382300

Abstract:

A method and system for scaling an image in accordance with the present invention is disclosed. The method utilizes a plurality of interpolators operating in parallel. Each interpolator operates with a different spatial offset with respect to the other. The final output is the average the output of each interpolator. Normally the initial value of the horizontal and vertical DDAs is zero. Offset is introduced by introducing an initial value in the DDA. Offset has the physical effect of manipulating the weights required for the averaging process in interpolation. Horizontal offset is the initial value in the Horizontal DDA while the vertical offset is the initial value in the Vertical DDA. The present invention relates to implementation in a semiconductor integrated circuit but the concepts can be used in software based image resizing (scaling) algorithms too.

US Patent:

6933937, Aug 23, 2005

Filed:

Aug 13, 2003

Appl. No.:

10/640699

Inventors:

Sandeep Agarwal - Fremont CA, US
Arun Johary - San Jose CA, US

Assignee:

Genesis Microchip Inc. - Alviso CA

International Classification:

G09G005/00

US Classification:

345213, 345611, 345643, 348536

Abstract:

Pixel clock frequency and optimum sampling phase adjustment is an important requirement in Flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency an optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from exsisting methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.

US Patent:

7205798, Apr 17, 2007

Filed:

Jan 28, 2005

Appl. No.:

11/045929

Inventors:

Sandeep Agarwal - Fremont CA, US
Xiaole Chen - San Jose CA, US

Assignee:

Intersil Americas Inc. - Milpitas CA

International Classification:

H03B 21/00

US Classification:

327105, 327107

Abstract:

Circuits, methods, and apparatus for reducing the phase error in an NCO clock output to reduce the clock jitter. This is particularly beneficial where the frequencies of the NCO output and reference signal are unrelated. One embodiment provides a circuit that corrects the phase of the NCO output in two steps in order to obtain a substantially glitch-free, high-speed operation. During the first step, the output of the NCO is phase shifted to the closest quarter portion of a cycle of a clock signal. A second correction step is then performed by steering a number of currents under the control of at least some of a number of remainder bits from the NCO. The current steering provides a die area efficient, low-noise phase correction. The decoded remainder bits are latched using a feed forward circuit that prevents the device from entering a locked state.

US Patent:

7498852, Mar 3, 2009

Filed:

Mar 15, 2007

Appl. No.:

11/686356

Inventors:

Sandeep Agarwal - Fremont CA, US
Xiaole Chen - San Jose CA, US

Assignee:

Intersil Americas Inc. - Milpitas CA

International Classification:

H03B 21/00

US Classification:

327105, 327106, 327107, 708101, 708271, 708276

Abstract:

Circuits, methods, and apparatus for adjusting an NCO output in order to provide a signal that is phase-locked to a reference signal. This is particularly beneficial where the frequencies of the NCO output and reference signal are unrelated. One embodiment provides a circuit that corrects the phase of the NCO output in two steps in order to reduce the chance of metastability. During the first, the output of the NCO is phase shifted to the closest correct portion of a cycle of a clock signal. A second correction is then performed by steering a number of currents under the control of at least some of a number of remainder bits from the NCO. The current steering provides a die area efficient, low-noise phase correction. The decoded remainder bits are latched using a feed forward circuit that prevents the device from entering a locked state.

US Patent:

7592846, Sep 22, 2009

Filed:

Dec 6, 2007

Appl. No.:

11/951565

Inventors:

Gustavo James Mehas - Sunnyvale CA, US
Sandeep Agarwal - Fremont CA, US
Jayant Vivrekar - San Jose CA, US
Xiaole Chen - San Jose CA, US

Assignee:

Intersil Americas Inc. - Milpitas CA

International Classification:

H03L 7/06

US Classification:

327158, 327149

Abstract:

A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.

US Patent:

7944192, May 17, 2011

Filed:

Aug 31, 2007

Appl. No.:

11/897681

Inventors:

Zaki Moussaoui - San Carlos CA, US
Sandeep Agarwal - Fremont CA, US
Jayant Vivrekar - San Jose CA, US

Assignee:

Intersil Americas Inc. - Milpitas CA

International Classification:

G05F 1/00

US Classification:

323282, 323222, 323271

Abstract:

An embodiment of a hysteretic power-supply controller includes a signal generator, frequency adjuster, and signal combiner. The signal generator is operable to generate a switching signal having a first level in response to a control signal being greater than a first reference value and having a second level in response to the control signal being less than a second reference value, the switching signal having an actual frequency and being operable to drive a switching stage that generates a regulated output signal. The frequency adjuster is operable to generate a frequency-adjust signal that is related to a difference between the actual frequency and a desired frequency. And the signal combiner is operable to generate the control signal from the frequency-adjust signal and the regulated output signal. Such a hysteretic power-supply controller may allow one to set the switching frequency to a desired value independently of the parameters of the power supply.

US Patent:

8108715, Jan 31, 2012

Filed:

Jul 2, 2010

Appl. No.:

12/830285

Inventors:

Sandeep Agarwal - Fremont CA, US

Assignee:

Symantec Corporation - Mountain View CA

International Classification:

G06F 11/00

US Classification:

714 10, 714 41, 714 12, 714 13, 714 25

Abstract:

A computer-implemented method for resolving split-brain scenarios in computer clusters may include (1) identifying a plurality of nodes within a computer cluster that are configured to collectively perform at least one task, (2) receiving, from a node within the computer cluster, a failure notification that identifies a link-based communication failure experienced by the node that prevents the nodes within the computer cluster from collectively performing the task, and, upon receiving the failure notification, (3) immediately prompting each node within the computer cluster to participate in an arbitration event in order to identify a subset of the nodes that is to assume responsibility for performing the task subsequent to the link-based communication failure. Various other methods, systems, and computer-readable media are also disclosed.

US Patent:

8159276, Apr 17, 2012

Filed:

Sep 22, 2009

Appl. No.:

12/564466

Inventors:

Gustavo James Mehas - Sunnyvale CA, US
Sandeep Agarwal - Fremont CA, US
Jayant Vivrekar - San Jose CA, US
Xiaole Chen - San Jose CA, US

Assignee:

Intersil Americas Inc. - Milpitas CA

International Classification:

H03L 7/06

US Classification:

327158, 327147

Abstract:

A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.