Shahriar Moinian

US Patent:

6657281, Dec 2, 2003

Filed:

Aug 3, 2000

Appl. No.:

09/631755

Inventors:

Yih-Feng Chyan - Orlando FL
Chunchieh Huang - Orlando FL
Chung Wai Leung - Orlando FL
Yi Ma - Orlando FL
Shahriar Moinian - Murray Hill NJ

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 27082

US Classification:

257591, 257565

Abstract:

The present invention provides a bipolar transistor located on a semiconductor wafer substrate. The bipolar transistor may comprise a collector located in the semiconductor wafer substrate, a base located in the collector, and an emitter located on the base and in contact with at least a portion of the base, wherein the emitter has a low K layer located therein. The low K layer may be, for example, located proximate a side of the emitter, or it may be located proximate opposing sides of the emitter. In all embodiments, however, the low K layer does not interfere with the proper functioning of the bipolar transistor, and substantially reduces the emitter-base capacitance typically associated with conventional bipolar transistors.

US Patent:

6825089, Nov 30, 2004

Filed:

Jun 4, 2003

Appl. No.:

10/454133

Inventors:

Shye Shapira - Allentown PA
Debra Johnson - Fleetwood PA
Shahriar Moinian - Murray Hill NJ

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 2120

US Classification:

438379, 257312, 257595, 257596, 257599, 257600

Abstract:

The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.

US Patent:

7174532, Feb 6, 2007

Filed:

Nov 18, 2004

Appl. No.:

10/992031

Inventors:

James D. Chlipala - Lower Macungie Township, Lehigh County PA, US
Shahriar Moinian - New Providence NJ, US

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

G06F 17/50

US Classification:

716 19, 716 20, 716 21

Abstract:

The present invention provides a method for manufacturing a semiconductor device, comprising: determining an isolation structure stress effect of a first semiconductor device, determining an optical proximity effect of a second semiconductor device, selecting a modeling design parameter such that the isolation structure stress effect is offset against the optical proximity effect on a fabrication model, and using the selected design parameter to construct a third semiconductor device.

US Patent:

7345354, Mar 18, 2008

Filed:

Aug 16, 2004

Appl. No.:

10/918981

Inventors:

Debra Johnson - Fleetwood PA, US
Shye Shapira - Allentown PA, US
Shahriar Moinian - Murray Hill NJ, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 29/76

US Classification:

257602, 257595

Abstract:

The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.

US Patent:

7480874, Jan 20, 2009

Filed:

Aug 5, 2005

Appl. No.:

11/198930

Inventors:

Kausar Banoo - Bethlehem PA, US
Seung H. Kang - Sinking Spring PA, US
Shahriar Moinian - New Providence NJ, US
Blane A. Musser - Topton PA, US
John A. Pantone - Birdsboro PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G06F 17/50

US Classification:

716 1, 716 4, 716 5

Abstract:

Techniques are presented for reliability analysis of integrated circuits. A circuit data file including a connectivity network with appended parasitic information is obtained. Circuit performance is simulated, based on the data file, to obtain simulated currents for metallic conductive paths of the circuit. Contextual representations of the paths are determined, and reliability analysis is performed on the contextual representations. The analysis can relate, for example, to electromigration, joule-heating, and/or fusing. The results of the analysis can be provided, for example, in the form of a report including recommended changes, such as width increases, to wires for which it is determined that reliability issues exist.

US Patent:

7847666, Dec 7, 2010

Filed:

Sep 27, 2006

Appl. No.:

11/535501

Inventors:

Shahriar Moinian - New Providence NJ, US
John E. Scoggins - Dover NH, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01F 5/00

US Classification:

336200, 336223, 336232

Abstract:

An inductor device in an integrated circuit includes a first winding portion, a bridge portion and a second winding portion. The integrated circuit has a first, a second, a third and a fourth metallization level. The first winding portion comprises a first metal line formed on the first metallization level and a second metal line formed on the second metallization level, the first metal line being electrically connected in parallel with the second metal line. The bridge portion comprises a third metal line formed on the third metallization level and a fourth metal line formed on the fourth metallization level, the third metal line being electrically connected in parallel with the fourth metal line. The second winding portion comprises a fifth metal line formed on the first metallization level and a sixth metal line formed on the second metallization level, the fifth metal line being electrically connected in parallel with the sixth metal line. The bridge portion electrically connects the first winding portion to the second winding portion.

US Patent:

8143696, Mar 27, 2012

Filed:

Mar 18, 2009

Appl. No.:

12/516301

Inventors:

Weiwei Mao - Macungie PA, US
Shahriar Moinian - New Providence NJ, US
Kenneth Wade Paist - Spring City PA, US
William B. Wilson - Macungie PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 27/08

US Classification:

257531, 257528, 438381, 361782

Abstract:

An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.

US Patent:

8283713, Oct 9, 2012

Filed:

Mar 14, 2011

Appl. No.:

13/046973

Inventors:

John G. Jansen - Macungie PA, US
Chi-Yi Kao - San Jose CA, US
Ce Chen - Milpitas CA, US
Shahriar Moinian - New Providence NJ, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 27/108

US Classification:

257296, 257211, 438622

Abstract:

An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.