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Sinjeet D Parekh

age ~46

from San Jose, CA

Also known as:
  • P M
Phone and address:
291 Dondero Way, San Jose, CA 95119

Sinjeet Parekh Phones & Addresses

  • 291 Dondero Way, San Jose, CA 95119
  • 4601 63Rd St, San Diego, CA 92115
  • 6271 Madeline St, San Diego, CA 92115
  • Sunnyvale, CA
  • Mountain View, CA

Us Patents

  • Phase Cancellation In A Phase-Locked Loop

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  • US Patent:
    20200321969, Oct 8, 2020
  • Filed:
    Jun 23, 2020
  • Appl. No.:
    16/908786
  • Inventors:
    - Dallas TX, US
    Christopher Andrew SCHELL - Tacoma WA, US
    Arvind SRIDHAR - Issaquah WA, US
    Sinjeet Dhanvantray PAREKH - San Jose CA, US
  • International Classification:
    H03L 7/093
    H03L 7/14
    H03L 7/087
    H03L 7/083
  • Abstract:
    A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.
  • Cycle Slip Detection And Correction In Phase-Locked Loop

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  • US Patent:
    20200177192, Jun 4, 2020
  • Filed:
    Feb 4, 2020
  • Appl. No.:
    16/780957
  • Inventors:
    - Dallas TX, US
    Christopher Andrew SCHELL - Tacoma WA, US
    Sinjeet Dhanvantray PAREKH - San Jose CA, US
  • International Classification:
    H03L 7/099
    H03L 7/083
    H03L 7/093
    G04F 10/00
  • Abstract:
    A digital phase-locked loop (DPLL) includes a voltage-controlled oscillator to generate an output clock, a filter coupled to the voltage-controlled oscillator, and a time-to-digital converter (TDC) that receives a reference clock and a feedback clock. The feedback clock is derived from the output clock. The TDC generates a digital output value. The DPLL also includes a cycle slip detector circuit coupled to the TDC. The cycle slip detector circuit detects a cycle slip based on the digital output value and adjusts the digital output value by a second digital value that corresponds to an integer multiple of a period of the reference clock.
  • Phase Cancellation In A Phase-Locked Loop

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  • US Patent:
    20200021301, Jan 16, 2020
  • Filed:
    Sep 25, 2019
  • Appl. No.:
    16/582341
  • Inventors:
    - Dallas TX, US
    Christopher Andrew SCHELL - Tacoma WA, US
    Arvind SRIDHAR - Issaquah WA, US
    Sinjeet Dhanvantray PAREKH - San Jose CA, US
  • International Classification:
    H03L 7/093
    H03L 7/083
    H03L 7/087
    H03L 7/14
  • Abstract:
    A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.
  • Time-To-Digital Converter Circuit

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  • US Patent:
    20190339650, Nov 7, 2019
  • Filed:
    May 29, 2018
  • Appl. No.:
    15/991020
  • Inventors:
    - Dallas TX, US
    Sinjeet Dhanvantray PAREKH - San Jose CA, US
  • International Classification:
    G04F 10/00
    H03L 7/197
  • Abstract:
    A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.
  • Time-To-Digital Converter Circuit

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  • US Patent:
    20190339651, Nov 7, 2019
  • Filed:
    May 6, 2019
  • Appl. No.:
    16/403774
  • Inventors:
    - Dallas TX, US
    Sinjeet Dhanvantray PAREKH - San Jose CA, US
  • International Classification:
    G04F 10/00
    H03L 7/197
  • Abstract:
    A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.
  • Three Loop Phase-Locked Loop

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  • US Patent:
    20190288695, Sep 19, 2019
  • Filed:
    Dec 27, 2018
  • Appl. No.:
    16/233972
  • Inventors:
    - Dallas TX, US
    Arvind SRIDHAR - Issaquah WA, US
    Sinjeet Dhanvantray PAREKH - San Jose CA, US
  • International Classification:
    H03L 7/087
    H03L 7/099
    H03L 7/197
  • Abstract:
    A phase-locked loop (PLL) system includes a first PLL coupled to receive a first reference clock. The PLL system also includes a second PLL coupled to receive a second reference clock. The output of the second PLL is coupled to the first PLL, and the second PLL is configured to control the first PLL. The PLL system further includes a third PLL coupled to receive an input reference clock. The output of the third PLL is coupled to the second PLL. The third PLL is configured to control the second PLL.
  • Phase Cancellation In A Phase-Locked Loop

    view source
  • US Patent:
    20190280699, Sep 12, 2019
  • Filed:
    Dec 27, 2018
  • Appl. No.:
    16/233283
  • Inventors:
    - Dallas TX, US
    Christopher Andrew SCHELL - Tacoma WA, US
    Arvind SRIDHAR - Issaquah WA, US
    Sinjeet Dhanvantray PAREKH - San Jose CA, US
  • International Classification:
    H03L 7/093
    H03L 7/083
    H03L 7/087
    H03L 7/14
  • Abstract:
    A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.
  • Cycle Slip Detection And Correction In Phase-Locked Loop

    view source
  • US Patent:
    20190280700, Sep 12, 2019
  • Filed:
    Dec 13, 2018
  • Appl. No.:
    16/218970
  • Inventors:
    - Dallas TX, US
    Christopher Andrew SCHELL - Tacoma WA, US
    Sinjeet Dhanvantray PAREKH - San Jose CA, US
  • International Classification:
    H03L 7/099
    H03L 7/083
    H03L 7/093
    G04F 10/00
  • Abstract:
    A digital phase-locked loop (DPLL) includes a voltage-controlled oscillator to generate an output clock, a filter coupled to the voltage-controlled oscillator, and a time-to-digital converter (TDC) that receives a reference clock and a feedback clock. The feedback clock is derived from the output clock. The TDC generates a digital output value. The DPLL also includes a cycle slip detector circuit coupled to the TDC. The cycle slip detector circuit detects a cycle slip based on the digital output value and adjusts the digital output value by a second digital value that corresponds to an integer multiple of a period of the reference clock.

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