Siva G Narendra

US Patent:

6346803, Feb 12, 2002

Filed:

Nov 30, 2000

Appl. No.:

09/727173

Inventors:

Vaughn J. Grossnickle - Hillsboro OR
Siva G. Narendra - Beaverton OR
Vivek K. De - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G05F 316

US Classification:

323315

Abstract:

A current reference has two control transistors sized and biased to generate two control currents. The two control currents change over process variations such that the difference between the two currents remains substantially constant over process variations. A current mirror receives and mirrors the difference current to provide a substantially process-independent output current.

US Patent:

6366156, Apr 2, 2002

Filed:

Nov 30, 1999

Appl. No.:

09/451661

Inventors:

Siva G. Narendra - Beaverton OR
Vivek K. De - Beaverton OR
Shekhar Y. Borkar - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G05F 110

US Classification:

327534, 327537

Abstract:

In some embodiments, In some embodiments, the invention includes an electrical system having a functional unit block (FUB) including field effect transistors (FETs). A distributed forward body bias (FBB) voltage generation system provides at least one body bias signal to at least some of the FETs of the FUB such that the at least some of the FETs have a constant FBB. In some embodiments, the system includes a constant differential voltage generator and a distributed body bias generator to receive a set of differential signals from the constant differential voltage generator and provide at least one body bias signal to at least some of the FETs of the FUB such that the at least some of the FETs have a constant forward body bias. In some embodiments, the system includes multiple body bias generators coupled to corresponding FUBs receive a set of differential signals from a single constant differential voltage generator. In other embodiments, multiple constant differential voltage generators provide multiple sets of differential signals to multiple body bias generators coupled to corresponding FUBs.

US Patent:

6411156, Jun 25, 2002

Filed:

Dec 30, 1998

Appl. No.:

09/224575

Inventors:

Shekhar Y. Borkar - Beaverton OR
Vivek K. De - Beaverton OR
Ali Keshavarzi - Portland OR
Siva G. Narendra - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 301

US Classification:

327534, 327545

Abstract:

In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control a setting of a body bias signal to control body biases provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal being responsive to an input signal to the control circuitry. In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control settings of a body bias signal, a supply voltage signal, and a clock signal to control body biases, supply voltages, and clock frequencies provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal, supply voltage signal, and clock signal being responsive to an input signal to the control circuitry.

US Patent:

6429711, Aug 6, 2002

Filed:

Jun 30, 2000

Appl. No.:

09/608314

Inventors:

James W. Tschanz - Hillsboro OR
Manoj Sachdev - Waterloo, CA
Siva G. Narendra - Beaverton OR
Vivek K. De - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 3356

US Classification:

327211, 327201, 326 97, 36518905

Abstract:

A circuit including a data signal input to receive a data signal, a clock signal input to receive a clock signal, a clocking circuit to generate control clocks, and a multiple input conditional inverter to receive the data signal and control clocks, and to generate an output. The circuit also includes at least one stack node pre-charging transistor coupled to a high signal transfer node in the multiple input conditional inverter and at least one stack node pre-discharging transistor coupled to a low signal transfer node in the multiple input conditional inverter. A keeper circuit receives the output of the multiple input conditional inverter and a buffer circuit receives the output of the multiple input conditional inverter and generates the circuit output.

US Patent:

6429726, Aug 6, 2002

Filed:

Mar 27, 2001

Appl. No.:

09/820067

Inventors:

David W. Bruneau - Milwaukie OR
Siva G. Narendra - Beaverton OR
Vivek K. De - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G05F 324

US Classification:

327537

Abstract:

A method and apparatus provide a forward body bias (FBB) according to various embodiments, in which a supply voltage is divided into a number of dc voltages. One of these voltages is selected as a function of the supply voltage (as measured between a power supply line and a power return line). A constant FBB is generated based upon the selected dc voltage and applied to each bulk terminal of at least some of the field effect transistors (FETs) of a given conductivity type in a functional unit block (FUB) of an integrated circuit die.

US Patent:

6433624, Aug 13, 2002

Filed:

Nov 30, 2000

Appl. No.:

09/727176

Inventors:

Vaughn J. Grossnickle - Hillsboro OR
Siva G. Narendra - Beaverton OR
Vivek K. De - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G05F 110

US Classification:

327543

Abstract:

A threshold voltage generation circuit includes a control transistor, one or more load transistors, and a current mirror. The load transistors are diode-connected transistors that are operated in saturation. The source-to-gate voltage of the load transistors approximates the threshold voltage of the transistors over process and temperature. The operation of the circuit is affected by choosing a bias voltage for the control transistor, the sizes of the control transistor and load transistors, and the ratio of transistor sizes within the current mirror.

US Patent:

6445170, Sep 3, 2002

Filed:

Oct 24, 2000

Appl. No.:

09/694901

Inventors:

Amaresh Pangal - Hillsboro OR
Siva G. Narendra - Beaverton OR
Aaron K. Martin - Hillsboro OR
Stephen R. Mooney - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G05F 156

US Classification:

323315, 323317

Abstract:

A current reference with reduced sensitivity to process variations includes two current sources. The first current source has an output current that is sensitive to process variations. The second current source has, as a component of its input current, the output current of the first current source. The input current to the second current source is substantially constant because the process dependent component has been removed by the output current of the first current source. Variable resistors internal to the current source are set using a control loop circuit and an external resistor.

US Patent:

6445216, Sep 3, 2002

Filed:

May 14, 2001

Appl. No.:

09/855910

Inventors:

David W. Bruneau - Milwaukie OR
Siva G. Narendra - Beaverton OR
Vivek K. De - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 706

US Classification:

327 52, 327 55, 327537

Abstract:

A sense amplifier in which its output nodes provide a full voltage swing between the supply and return nodes. The sense amplifier further includes a reset circuit to selectively equalize the first and second output nodes. An output of the sense amplifier is coupled to either a digital logic gate or a flip-flop to receive the full swing. Each field effect transistor (FET) of the input pair in the sense amplifier is either zero body biased or forward body biased, so that a bulk-source junction of each FET is either zero biased or forward biased.

Author:

Siva Narendra

ISBN #:

0387257373

Author:

Siva G. Narendra

ISBN #:

0387281339