Sowmiya Jayachandran

US Patent:

20090044078, Feb 12, 2009

Filed:

Aug 8, 2007

Appl. No.:

11/835878

Inventors:

Andrew Vogan - Aloha OR, US
Jawad B. Khan - Hillsboro OR, US
Sowmiya Jayachandran - Portland OR, US

International Classification:

G06F 11/16
H03M 13/15

US Classification:

714773, 714782, 714784, 714E11062, 714E11001

Abstract:

A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffer memory may store the input data and associated error correcting data in at least one of the storage channels on a non-volatile storage media. An error correcting engine between the host controller and the buffer memory may perform error correction encoding on the input data from the host device to generate the associated error correcting data for storage in the buffer memory. Such error correcting engine may protect against data errors in the buffer memory and in the storage channels.

US Patent:

20090172213, Jul 2, 2009

Filed:

Dec 31, 2007

Appl. No.:

11/968042

Inventors:

Sowmiya Jayachandran - Portland OR, US
Jawad B. Khan - Hillsboro OR, US
Randall K. Webb - Hillsboro OR, US
Robert W. Faber - Hillsboro OR, US

International Classification:

G06F 3/00

US Classification:

710 19

Abstract:

In some embodiments, after a hold off time following issuance of a memory command has elapsed, a status read operation is performed to determine a status of the memory command. In some embodiments, if the memory command has not yet completed, a polling interval is used to perform a status read operation to determine the status of the memory command after the polling interval has expired, and repeating the process until the memory command has been completed. Other embodiments are described and claimed.

US Patent:

20200034061, Jan 30, 2020

Filed:

Sep 27, 2019

Appl. No.:

16/585801

Inventors:

- Santa Clara CA, US
Zvika GREENFIELD - Kfar Sava, IL
Sowmiya JAYACHANDRAN - Portland OR, US
Dimpesh PATEL - Surrey, CA

International Classification:

G06F 3/06
G06F 12/0862

Abstract:

A multilevel memory subsystem includes a persistent memory device that can access data chunks sequentially or randomly to improve read latency, or can prefetch data blocks to improve read bandwidth. A media controller dynamically switches between a first read mode of accessing data chunks sequentially or randomly and a second read mode of prefetching data blocks. The media controller switches between the first and second read modes based on a number of read commands pending in a command queue.

US Patent:

20200019227, Jan 16, 2020

Filed:

Sep 25, 2019

Appl. No.:

16/583141

Inventors:

- BOISE ID, US
William Low - Vancouver, CA
Sowmiya Jayachandran - Portland OR, US

Assignee:

MICRON TECHNOLOGY, INC. - BOISE ID

International Classification:

G06F 1/3206
G06F 13/42
G06F 1/3287
G06F 1/3234

Abstract:

According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification, The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.

US Patent:

20180068695, Mar 8, 2018

Filed:

Sep 13, 2017

Appl. No.:

15/703589

Inventors:

- Santa Clara CA, US
Frank T. HADY - Portland OR, US
Paul D. RUBY - Folsom CA, US
Kiran PANGAL - Fremont CA, US
Sowmiya JAYACHANDRAN - Portland OR, US

International Classification:

G11C 7/10
G11C 11/406
G11C 16/34

Abstract:

In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.

US Patent:

20170364135, Dec 21, 2017

Filed:

Aug 31, 2017

Appl. No.:

15/693209

Inventors:

- BOISE ID, US
William Low - Vancouver, CA
Sowmiya Jayachandran - Portland OR, US

Assignee:

MICRON TECHNOLOGY, INC. - BOISE ID

International Classification:

G06F 1/32
G06F 13/42

Abstract:

According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification. The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.

US Patent:

20170185136, Jun 29, 2017

Filed:

Dec 28, 2015

Appl. No.:

14/980592

Inventors:

- BOISE ID, US
William Low - Vancouver, CA
Sowmiya Jayachandran - Portland OR, US

International Classification:

G06F 1/32
G06F 13/42

Abstract:

According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification, The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.

US Patent:

20160189757, Jun 30, 2016

Filed:

Nov 11, 2015

Appl. No.:

14/938221

Inventors:

PRASHANT S. DAMLE - Portland OR, US
FRANK T. HADY - Portland OR, US
PAUL D. RUBY - Folsom CA, US
KIRAN PANGAL - Fremont CA, US
SOWMIYA JAYACHANDRAN - Portland OR, US

International Classification:

G11C 7/10
G11C 11/406

Abstract:

In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.