Sukanya Thiagarajan
age ~42
from San Jose, CA
- Also known as:
-
- Sukanya Phiagarajan
- Sukanya Thiagarasan
- Thiagarajan Sukanya
- Phone and address:
-
2397 Lost Oaks Dr, San Jose, CA 95124
6086280708
Sukanya Thiagarajan Phones & Addresses
- 2397 Lost Oaks Dr, San Jose, CA 95124 • 6086280708
- Santa Clara, CA
- El Dorado Hills, CA
- 4701 Monterey Oaks Blvd, Austin, TX 78749 • 5124946474
- Madison, WI
Work
-
Company:SynopsysNov 2017
-
Position:Test applications engineer
Education
-
Degree:Master of Science, Masters
-
School / High School:University of Wisconsin - MadisonDec 2005
Skills
Atpg • Dft • Jtag • Verilog • Debugging • Soc • Fastscan • Vlsi • Rtl Design • Microprocessors • Computer Architecture • Asic • Eda • Simulations • Rtl Verification • Static Timing Analysis • Application Specific Integrated Circuits • System on A Chip
Languages
English • Tamil • Hindi
Industries
Computer Software
Resumes
Test Applications Engineer
view sourceLocation:
2397 Lost Oaks Dr, San Jose, CA 95124
Industry:
Computer Software
Work:
Synopsys
Test Applications Engineer
Intel Corporation Dec 2015 - Nov 2017
Server Validation
Amd May 2011 - Sep 2015
Mts Engineer Dft and Atpg at Advanced Micro Devices
Amd Mar 2008 - May 2011
Senior Design Engineer Dft and Atpg
Amd Feb 2006 - Mar 2008
Design Engineer
Test Applications Engineer
Intel Corporation Dec 2015 - Nov 2017
Server Validation
Amd May 2011 - Sep 2015
Mts Engineer Dft and Atpg at Advanced Micro Devices
Amd Mar 2008 - May 2011
Senior Design Engineer Dft and Atpg
Amd Feb 2006 - Mar 2008
Design Engineer
Education:
University of Wisconsin - Madison Dec 2005
Master of Science, Masters University of Wisconsin - Madison 2003 - 2005
University of Madras Jun 2003
University of Madras 1999 - 2003
Bachelor of Engineering, Bachelors, Engineering
Master of Science, Masters University of Wisconsin - Madison 2003 - 2005
University of Madras Jun 2003
University of Madras 1999 - 2003
Bachelor of Engineering, Bachelors, Engineering
Skills:
Atpg
Dft
Jtag
Verilog
Debugging
Soc
Fastscan
Vlsi
Rtl Design
Microprocessors
Computer Architecture
Asic
Eda
Simulations
Rtl Verification
Static Timing Analysis
Application Specific Integrated Circuits
System on A Chip
Dft
Jtag
Verilog
Debugging
Soc
Fastscan
Vlsi
Rtl Design
Microprocessors
Computer Architecture
Asic
Eda
Simulations
Rtl Verification
Static Timing Analysis
Application Specific Integrated Circuits
System on A Chip
Languages:
English
Tamil
Hindi
Tamil
Hindi
Mylife
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