Suresh B Kariyadan

US Patent:

20120187928, Jul 26, 2012

Filed:

May 19, 2011

Appl. No.:

13/111638

Inventors:

Parviz Parto - Laguna Niguel CA, US
Seungbeom Kevin Kim - Cerritos CA, US
Amir M. Rahimi - Irvine CA, US
Suresh Kariyadan - Irvine CA, US

Assignee:

INTERNATIONAL RECTIFIER CORPORATION - EL SEGUNDO CA

International Classification:

G05F 1/46

US Classification:

323271

Abstract:

According to one embodiment, a synchronous buck converter comprises a multi-mode control circuit for detecting a load condition of a variable load, an output stage driven by the multi-mode control circuit, wherein the variable load is coupled to the output stage, and a feedback circuit connected between the output stage and the multi-mode control circuit. The multi-mode control circuit is configured to adjust a current provided by the output stage to the variable load based on the load condition. In one embodiment, the multi-mode control circuit selectably uses one of at least a first control mode and a second control mode according to the load condition, wherein the first control mode is a pulse-width modulation (PWM) mode selected for switching efficiency when the load condition is heavy and the second control mode is an adaptive ON-time (AOT) mode selected for switching efficiency when the load condition is light.

US Patent:

20180145594, May 24, 2018

Filed:

Jun 23, 2017

Appl. No.:

15/631811

Inventors:

- Cupertino CA, US
Suresh B. Kariyadan - San Jose CA, US
Vincent W. Trimeloni - Cupertino CA, US

International Classification:

H02M 3/158
H02M 1/084
H03K 7/08

Abstract:

A module stack includes a lower module, a middle module above the lower module, and an upper module above the middle module. The lower module has power stage control circuitry configured to convert a PWM input signal into phase driver control signals, and power stages to be controlled by the phase driver control signals, respectively. The middle module has phase inductors each having a respective winding and a respective magnetic core. The respective winding has one end joined to a respective one of the power stages in the lower module and another end joined to a common node in the middle module. The upper module has a current sense resistor that has one end joined to the common node in the middle module and another end joined to an output node in the upper module. Other embodiments are also described and claimed.