Sushil Kumar

Author:

Sushil Kumar

ISBN #:

0210405031

Author:

Sushil Kumar

ISBN #:

8172360959

Author:

Sushil Kumar

ISBN #:

8175100753

Author:

Sushil Kumar

ISBN #:

8179860329

Author:

Sushil Kumar

ISBN #:

8185268843

Author:

Sushil Kumar

ISBN #:

8186867295

US Patent:

6831616, Dec 14, 2004

Filed:

Jun 4, 2003

Appl. No.:

10/455272

Inventors:

Michael Wendell Vice - El Granada CA
Sushil Kumar - Milpitas CA

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

H01Q 150

US Classification:

343859, 333 26

Abstract:

A transmission line balun eliminates unwanted reflection of signal energy coupling to a ground plane. A junction of the conductive segments connected to the unbalanced port on the balun is connected to the ground plane with a resistor. The selected junction is a virtual ground of the balun, so the presence of the resistor does not degrade the balun performance. The resistor dissipates the energy from the parasitic mode propagating with the ground plane so that no signal is reflected back to short out the signal source. The value of the resistor is selected to facilitate maximum termination of the parasitic mode propagation.

US Patent:

7020599, Mar 28, 2006

Filed:

Dec 13, 2001

Appl. No.:

10/017337

Inventors:

Qiang Cao - Burlingame CA, US
Sushil Kumar - Mountain View CA, US
Tirthankar Lahiri - Santa Clara CA, US
Yunrui Li - Fremont CA, US
Gianfranco Putzolu - San Francisco CA, US

Assignee:

Oracle International Corporation (OIC) - Redwood Shores CA

International Classification:

G06F 9/45

US Classification:

703 22, 714 6, 714 15, 713200, 707202, 707206, 707102

Abstract:

A method for simulating different MTTR settings includes determining a simulated MTTR setting and providing a simulated checkpoint queue. The simulated checkpoint queue is associated with the simulated MTTR setting and is an ordered list of one or more elements. Each element represents a buffer, and the ordered list has a head and a tail. The method also includes providing a simulated write counter associated with the simulated MTTR setting. The method further includes, in response to detecting a change to a first buffer, checking if the first buffer is represented in the simulated checkpoint queue. If the first buffer is not represented in the simulated checkpoint queue, an element that represents the first buffer is linked to the tail of the simulated checkpoint queue. An MTTR advisory system includes a memory, one or more processors coupled to the memory, a simulated MTTR setting, a simulated checkpoint queue, and a simulated write counter. The simulated MTTR setting is maintained in the memory.

US Patent:

7525385, Apr 28, 2009

Filed:

Oct 30, 2006

Appl. No.:

11/589177

Inventors:

Sushil Kumar - Fremont CA, US

Assignee:

Avago Technologies Wireless IP (Singapore) Pte. Ltd. - Singapore

International Classification:

H03F 3/68

US Classification:

330295, 330 54, 330 43

Abstract:

A traveling wave amplifier includes a synthetic gate line, a synthetic drain line and a plurality of common drain driven cascode transistor circuits each connected between the synthetic gate line and the synthetic drain line.

US Patent:

7526508, Apr 28, 2009

Filed:

Sep 3, 2004

Appl. No.:

10/934076

Inventors:

Leng Leng Tan - Sunnyvale CA, US
Gianfranco Putzolu - San Francisco CA, US
Richard Sarwal - Portola Valley CA, US
Alex Tsukerman - Foster City CA, US
Gary C. Ngai - Saratoga CA, US
Graham Stephen Wood - El Granada CA, US
Karl Dias - Foster City CA, US
Mark Ramacher - San Carlos CA, US
Benoit Dageville - Foster City CA, US
Mohamed Ziauddin - Pleasanton CA, US
Tirthankar Lahiri - Santa Clara CA, US
Sujatha Muthulingam - Mountain View CA, US
Vishwanath Karra - San Jose CA, US
Francisco Sanchez - San Carlos CA, US
Hsiao-Te Su - Milpitas CA, US
Wanli Yang - San Mateo CA, US
Vasudha Krishnaswamy - Fremont CA, US
Sushil Kumar - San Jose CA, US

Assignee:

Oracle International Corporation - Redwood Shores CA

International Classification:

G06F 17/30

US Classification:

707200, 707 2

Abstract:

An intelligent database infrastructure wherein the management of all database components is performed by and within the database itself by integrating management of various components with a central management control. Each individual database component, as well as the central management control, is self-managing. A central management control module integrates and interacts with the various database components. The database is configured to automatically tune to varying workloads and configurations, correct or alert about bad conditions, and advise on ways to improve overall system performance.

US Patent:

7774312, Aug 10, 2010

Filed:

Sep 3, 2004

Appl. No.:

10/934771

Inventors:

Gary Ngai - Saratoga CA, US
Michael Feng - San Mateo CA, US
Alex Tsukerman - Foster City CA, US
Benoit Dageville - Foster City CA, US
Mark Ramacher - San Carlos CA, US
Karl Dias - Foster City CA, US
Graham S. Wood - El Granada CA, US
Leng Leng Tan - Sunnyvale CA, US
Richard Sarwal - Portola Valley CA, US
Sushil Kumar - San Jose CA, US

Assignee:

Oracle International Corporation - Redwood Shores CA

International Classification:

G06F 17/30

US Classification:

707637, 707649, 707688

Abstract:

A self-managing workload repository (AWR) infrastructure useful for a database server to collect and manage selected sets of important system performance statistics. Based on a schedule, the AWR runs automatically to collect data about the operation of the database system, and stores the data that it captures into the database. The AWR is advantageously designed to be lightweight and to self manage its use of storage space so as to avoid ending up with a repository of performance data that is larger than the database that it is capturing data about. The AWR is configured to automatically capture snapshots of statistics data on a periodic basis as well as purge stale data on a periodic basis. Both the frequency of the statistics data capture and length of time for which data is kept is adjustable. Manual snapshots and purging may also be performed.

US Patent:

8024301, Sep 20, 2011

Filed:

Aug 11, 2004

Appl. No.:

10/916695

Inventors:

Karl Dias - Foster City CA, US
Graham S. Wood - El Granada CA, US
Shivani Gupta - Los Altos CA, US
Sushil Kumar - San Jose CA, US
Mark Ramacher - San Carlos CA, US
Uri Shaft - Castro Valley CA, US
Leng Leng Tan - Sunnyvale CA, US
Venkateshwaran Venkataramani - Redwood City CA, US

Assignee:

Oracle International Corporation - Redwood Shores CA

International Classification:

G06F 7/00

US Classification:

707688, 707792

Abstract:

One or more usage models are provided for a database. Each usage model includes a set of rules that are used to analyze database performance. A usage model in one or more usage models is determined. Database information is determined based on the usage model. The database information is then analyzed based on rules associated with the usage model. One or more performance problems are determined based on the analysis.

US Patent:

8131248, Mar 6, 2012

Filed:

Oct 2, 2008

Appl. No.:

12/244091

Inventors:

Sushil Kumar - Fremont CA, US

Assignee:

Avago Technologies Wireless IP (Singapore) Pte. Ltd. - Singapore

International Classification:

H04B 1/26

US Classification:

455318, 455334, 333125

Abstract:

A feed-forward device is provided for a mixer including a diplexer having a radio frequency port, an intermediate frequency port, and a common port; and a mixing circuit receiving an in-phase local oscillator signal and an out-of-phase local oscillator signal and having an output coupled to the common port of the diplexer. The feed-forward device includes: a first signal sampler having an input adapted to sample the in-phase local oscillator signal and to output a sampled in-phase local oscillator signal; a second signal sampler having an input adapted to sample the out-of-phase local oscillator signal and to output a sampled out-of-phase local oscillator signal; and an arrangement for coupling the sampled in-phase local oscillator signal and the sampled out-of-phase local oscillator signal to the common port of the diplexer.

US Patent:

20220223207, Jul 14, 2022

Filed:

Nov 9, 2021

Appl. No.:

17/522214

Inventors:

- Singapore, SG
Sushil Kumar - San Jose CA, US
Gajanan Sahebrao Jedhe - San Jose CA, US
Ritesh Garg - San Jose CA, US
Gaurang Prabhakar Narvekar - San Jose CA, US

International Classification:

G11C 15/04

Abstract:

A content addressable memory (CAM) device includes multiple CAM sub-banks Each CAM sub-bank includes an array of CAM cells arranged in rows and columns and partitioned into a first stage and a second stage along a column dimension. Each CAM sub-bank further includes first-stage match lines (MLs), first-stage search line (SL) pairs, second-stage MLs, and second-stage SL pairs. Each second-stage SL pair is coupled to a column of CAM cells in the second stage and is gated by an SL enable (SL_EN signal). Each CAM sub-bank further includes a circuit operative to receive all of the first-stage MLs as input and de-assert the SL_EN signal when none of the first-stage MLs indicate a match. De-assertion of the SL_EN signal blocks a second portion search key from being provided to the second-stage SL pairs.

Address:

5400 Hellyer Ave, San Jose, CA 95138

VIN:

JHLRE487X7C046139

Make:

HONDA

Model:

CR-V

Year:

2007