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Tanuj Saxena

age ~36

from Chandler, AZ

Tanuj Saxena Phones & Addresses

  • Chandler, AZ
  • Tempe, AZ
  • Troy, NY

Education

  • School / High School:
    Indian Institute of Technology Bombay
    2006
  • Specialities:
    Bachelor of Technology in Engineering Physics

Resumes

Tanuj Saxena Photo 1

Power Device Design Engineer

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Location:
Albany, NY
Industry:
Semiconductors
Work:
Nxp Semiconductors
Power Device Design Engineer

Freescale Semiconductor Aug 1, 2015 - Dec 2015
Power Device Design Engineer

Rensselaer Polytechnic Institute Aug 2010 - Aug 2015
Research Assistant

Smart Lighting Erc Jun 2014 - Jul 2014
Instructor
Education:
Rensselaer Polytechnic Institute 2010 - 2015
Doctorates, Doctor of Philosophy, Electrical Engineering
Indian Institute of Technology, Bombay 2006 - 2010
Skills:
Semiconductor Fabrication
Physics
Python
Matlab
Photolithography
Electrical and Optical Characterization of Electronic Devices
Operation and Maintenance of Laser and Spectroscopic Systems
Semiconductor Device
Photoluminescence
I V
C V
C++
Atmel Avr
Laser Applications
Latex
Sentaurus Tcad
Medici
Tsuprem
Cadence Spectre
Interests:
Politics
Cooking
Photography
Languages:
English
Hindi
Urdu
Tanuj Saxena Photo 2

Tanuj Saxena

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Tanuj Saxena Photo 3

Tanuj Saxena Troy, NY

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Education:
Indian Institute of Technology Bombay
2006 to 2010
Bachelor of Technology in Engineering Physics
Rensselaer Polytechnic Institute
2010
PhD in Electrical Engineering

Us Patents

  • Mirror Device Structure For Power Mosfet And Method Of Manufacture

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  • US Patent:
    20200373426, Nov 26, 2020
  • Filed:
    May 20, 2019
  • Appl. No.:
    16/417243
  • Inventors:
    - Austin TX, US
    Feng Li - Austin TX, US
    Vishnu Khemka - Chandler AZ, US
    Moaniss Zitouni - Gilbert AZ, US
    Tanuj Saxena - Chandler AZ, US
  • International Classification:
    H01L 29/78
    H01L 27/088
    H01L 29/10
    H01L 29/66
    H01L 21/8234
  • Abstract:
    A MOSFET includes a substrate having a body region of a first conductivity type. A main field effect transistor (mainFET) and a mirror device are formed in the substrate. The mainFET includes first gate trenches, first source regions of a second conductivity type adjacent to the first gate trenches, and first body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the first source regions. The mirror device includes second gate trenches, second source regions of the second conductivity type adjacent to the second gate trenches, second body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the second source regions, and link elements of the first conductivity type interconnecting pairs of the second body implant regions.
  • Die With Buried Doped Isolation Region

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  • US Patent:
    20200075393, Mar 5, 2020
  • Filed:
    Aug 30, 2018
  • Appl. No.:
    16/116986
  • Inventors:
    - AUSTIN TX, US
    Tanuj Saxena - Chandler AZ, US
    Ljubo Radic - Gilbert AZ, US
    Bernhard Grote - Phoenix AZ, US
  • International Classification:
    H01L 21/761
    H01L 21/762
    H01L 21/78
    H01L 21/265
  • Abstract:
    A continuous buried doped isolation region in a substrate of a die. The substrate includes an isolation ring structure surrounding a first area of the die. The continuous buried doped isolation region is of a net first conductivity type and is located in the first area. The continuous buried doped isolation region including a first portion having a net first conductivity type dopant concentration of at least a first level located in an interior region of the first area and extending to a sidewall of the isolation ring structure. The first portion does not extend to the sidewall of the isolation ring structure in a location of a corner area of the first area. The corner area is defined by the isolation ring structure. A second portion of the continuous buried doped isolation region in the corner area has a net first conductivity type dopant concentration of a second level that is lower than the first level. The die comprises a semiconductor device located in the first area and including components located in the substrate in the first area above the continuous buried doped isolation region.

Myspace

Tanuj Saxena Photo 4

Tanuj Saxena

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Locality:
India
Gender:
Male
Birthday:
1948

Facebook

Tanuj Saxena Photo 5

Tanuj Saxena

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Tanuj Saxena Photo 6

Tanuj Saxena

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Tanuj Saxena Photo 7

Tanuj Saxena

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Tanuj Saxena Photo 8

Tanuj Saxena

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Tanuj Saxena Photo 9

Tanuj Saxena

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Tanuj Saxena Photo 10

Tanuj Saxena

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Tanuj Saxena Photo 11

Tanuj Saxena

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Tanuj Saxena Photo 12

Tanuj Saxena

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Youtube

DIT ROCKERZZ

  • Category:
    Entertainment
  • Uploaded:
    08 Dec, 2010
  • Duration:
    6m 1s

Googleplus

Tanuj Saxena Photo 13

Tanuj Saxena

Lived:
Jaipur, India
Mumbai, India
Troy, NY
Education:
Rensselaer Polytechnic Institute - Electrical Engineering, Indian Institute of Technology Bombay - Engineering Physics
Tanuj Saxena Photo 14

Tanuj Saxena

Work:
Frito-Lay at PSR
Education:
M J P R University
Tanuj Saxena Photo 15

Tanuj Saxena

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Tanuj Saxena

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Tanuj Saxena

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Tanuj Saxena

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Tanuj Saxena

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Tanuj Saxena


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