Tiruchirapalli N Arunagiri

US Patent:

7884017, Feb 8, 2011

Filed:

Feb 3, 2010

Appl. No.:

12/699518

Inventors:

Zhonghui Alex Wang - San Jose CA, US
Tiruchirapalli Arunagiri - Newark CA, US
Fritz C. Redeker - Fremont CA, US
Yezdi Dordi - Palo Alto CA, US
John Boyd - Ottawa, CA
Mikhail Korolik - San Jose CA, US
Arthur M. Howald - Pleasanton CA, US
William Thie - Sunnyvale CA, US
Praveen Nalla - Fremont CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21/44
H01L 21/31
H01L 21/469
H01L 21/24
H01L 21/40

US Classification:

438678, 438540, 438770

Abstract:

Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to form a cupric oxide layer. The thermal treatment in the reducing environment then reduces the cupric oxide to elemental copper. This leaves the exposed copper clean and in condition for further processing, such as electroless plating.

US Patent:

8026605, Sep 27, 2011

Filed:

Dec 14, 2006

Appl. No.:

11/638413

Inventors:

Yezdi Dordi - Palo Alto CA, US
John M. Boyd - Hillsboro OR, US
Fritz C. Redeker - Fremont CA, US
William Thie - Mountain View CA, US
Tiruchirapalli Arunagiri - Fremont CA, US
Hyungsuk Alexander Yoon - San Jose CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 23/535
H01L 21/4763

US Classification:

257751, 257752, 257753, 257E23141, 257E23155, 257E23161, 257E21584, 438643

Abstract:

An interconnect structure is provided, including a layer of dielectric material having at least one opening and a first barrier layer on sidewalls defining the opening. A ruthenium-containing second barrier layer overlays the first barrier layer, the second barrier layer having a ruthenium zone, a ruthenium oxide zone, and a ruthenium-rich zone. The ruthenium zone is interposed between the first barrier layer and the ruthenium oxide zone. The ruthenium oxide zone is interposed between the ruthenium zone and the ruthenium-rich zone.

US Patent:

8069813, Dec 6, 2011

Filed:

Apr 16, 2007

Appl. No.:

11/735984

Inventors:

William Thie - Mountain View CA, US
John M. Boyd - Woodlawn, CA
Fritz C. Redeker - Fremont CA, US
Yezdi Dordi - Palo Alto CA, US
John Parks - Hercules CA, US
Tiruchirapalli Arunagiri - Fremont CA, US
Aleksander Owczarz - San Jose CA, US
Todd Balisky - Corona CA, US
Clint Thomas - Milpitas CA, US
Jacob Wylie - Fremont CA, US
Alan M. Schoepp - Ben Lomond CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

B05C 3/00

US Classification:

118423, 118 58, 118 66, 118429, 118500, 438678, 438687

Abstract:

A dry-in/dry-out system is disclosed for wafer electroless plating. The system includes an upper zone for wafer ingress/egress and drying operations. Proximity heads are provided in the upper zone to perform the drying operations. The system also includes a lower zone for electroless plating operations. The lower zone includes an electroless plating apparatus that implements a wafer submersion by fluid upwelling method. The upper and lower zones of the system are enclosed by a dual-walled chamber, wherein the inner wall is a chemically inert plastic and the outer wall is a structural metal. The system interfaces with a fluid handling system which provides the necessary chemistry supply and control for the system. The system is ambient controlled. Also, the system interfaces with an ambient controlled managed transfer module (MTM).

US Patent:

8133812, Mar 13, 2012

Filed:

Sep 18, 2009

Appl. No.:

12/562955

Inventors:

Yezdi Dordi - Palo Alto CA, US
John Boyd - Hillsboro OR, US
Fritz Redeker - Fremont CA, US
William Thie - Mountain View CA, US
Tiruchirapalli Arunagiri - Fremont CA, US
Alex Yoon - San Jose CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21/44
H01L 21/4763

US Classification:

438687, 438650, 257E21584, 257E21585

Abstract:

This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the method includes forming the barrier layer on a surface of a substrate and subjecting the barrier layer to a process condition so as to form a removable passivated surface on the barrier layer. The method further includes removing the passivated surface from the barrier layer and depositing the gapfill copper layer onto the barrier layer. Another aspect of the present invention is an integrated system for depositing a copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the integrated system comprises at least one process module configured for barrier layer deposition and passivated surface formation and at least one other process module configured for passivated surface removal and deposition of copper onto the barrier layer. The system further includes at least one transfer module coupled so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.

US Patent:

8241701, Aug 14, 2012

Filed:

Aug 30, 2006

Appl. No.:

11/514038

Inventors:

Yezdi Dordi - Palo Alto CA, US
John Boyd - Hillsboro OR, US
Tiruchirapalli Arunagiri - Fremont CA, US
Hyungsuk Alexander Yoon - San Jose CA, US
Fritz C. Redeker - Fremont CA, US
William Thie - Mountain View CA, US
Arthur M. Howald - Pleasanton CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

B05D 5/12

US Classification:

427 981, 427 979

Abstract:

The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve metal-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce an improved metal-to-metal interface, more specifically barrier-to-copper interface. An exemplary method of preparing a substrate surface of a substrate to deposit a metallic barrier layer to line a copper interconnect structure of the substrate and to deposit a thin copper seed layer on a surface of the metallic barrier layer in an integrated system to improve electromigration performance of the copper interconnect is provided. The method includes cleaning an exposed surface of a underlying metal to remove surface metal oxide in the integrated system, wherein the underlying metal is part of a underlying interconnect electrically connected to the copper interconnect. The method also includes depositing the metallic barrier layer to line the copper interconnect structure in the integrated system, wherein after depositing the metallic barrier layer, the substrate is transferred and processed in controlled environment to prevent the formation of metallic barrier oxide. The method further includes depositing the thin copper seed layer in the integrated system, and depositing a gap-fill copper layer over the thin copper seed layer in the integrated system.

US Patent:

8314027, Nov 20, 2012

Filed:

Oct 28, 2011

Appl. No.:

13/284709

Inventors:

William Thie - Mountain View CA, US
John M. Boyd - Woodlawn, CA
Fritz C. Redeker - Fremont CA, US
Yezdi Dordi - Palo Alto CA, US
John Parks - Hercules CA, US
Tiruchirapalli Arunagiri - Fremont CA, US
Aleksander Owczarz - San Jose CA, US
Todd Balisky - Corona CA, US
Clint Thomas - Milpitas CA, US
Jacob Wylie - Fremont CA, US
Alan M. Schoepp - Ben Lomond CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21/30
C25D 1/00

US Classification:

438678, 438800, 20429826

Abstract:

A dry-in/dry-out system is disclosed for wafer electroless plating. The system includes an upper zone for wafer ingress/egress and drying operations. Proximity heads are provided in the upper zone to perform the drying operations. The system also includes a lower zone for electroless plating operations. The lower zone includes an electroless plating apparatus that implements a wafer submersion by fluid upwelling method. The upper and lower zones of the system are enclosed by a dual-walled chamber, wherein the inner wall is a chemically inert plastic and the outer wall is a structural metal. The system interfaces with a fluid handling system which provides the necessary chemistry supply and control for the system. The system is ambient controlled. Also, the system interfaces with an ambient controlled managed transfer module (MTM).

US Patent:

8404626, Mar 26, 2013

Filed:

Dec 13, 2008

Appl. No.:

12/334462

Inventors:

Artur Kolics - Dublin CA, US
Shijian Li - San Jose CA, US
Tiruchirapalli Arunagiri - Newark CA, US
William Thie - Mountain View CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

C11D 3/26
C11D 3/20
C11D 3/43
C09K 13/00

US Classification:

510175, 510178, 510245, 510258, 510434, 510477, 510488, 510499, 510505

Abstract:

One embodiment of the present invention is a method of fabricating an integrated circuit. The method includes providing a substrate having a metal and dielectric damascene metallization layer and depositing substantially on the metal a cap. After deposition of the cap, the substrate is cleaned with a solution comprising an amine to provide a pH for the cleaning solution of 7 to about 13. Another embodiment of the presented invention is a method of cleaning substrates. Still another embodiment of the present invention is a formulation for a cleaning solution.

US Patent:

8485120, Jul 16, 2013

Filed:

Apr 16, 2007

Appl. No.:

11/735987

Inventors:

William Thie - Mountain View CA, US
John M. Boyd - Woodlawn, CA
Fritz C. Redeker - Fremont CA, US
Yezdi Dordi - Palo Alto CA, US
John Parks - Hercules CA, US
Tiruchirapalli Arunagiri - Fremont CA, US
Aleksander Owczarz - San Jose CA, US
Todd Balisky - Corona CA, US
Clint Thomas - Milpitas CA, US
Jacob Wylie - Fremont CA, US
Alan M. Schoepp - Ben Lomond CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

B05C 11/00
B05D 1/28

US Classification:

118 64, 4274301

Abstract:

A semiconductor wafer electroless plating apparatus includes a platen and a fluid bowl. The platen has a top surface defined to support a wafer, and an outer surface extending downward from a periphery of the top surface to a lower surface of the platen. The fluid bowl has an inner volume defined by an interior surface so as to receive the platen, and wafer to be supported thereon, within the inner volume. A seal is disposed around the interior surface of the fluid bowl so as to form a liquid tight barrier when engaged between the interior surface of the fluid bowl and the outer surface of the platen. A number of fluid dispense nozzles are positioned to dispense electroplating solution within the fluid bowl above the seal so as to rise up and flow over the platen, thereby flowing over the wafer when present on the platen.