Toshinari Takayanagi

US Patent:

6885610, Apr 26, 2005

Filed:

Apr 11, 2003

Appl. No.:

10/411928

Inventors:

Toshinari Takayanagi - San Jose CA, US

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G11C008/00

US Classification:

365233, 365194, 36518902

Abstract:

A system and method for adjusting the clock delay in a self-timed memory system having a memory array and a sense amplifier includes a programmable delay circuit coupled as an input to the sense amplifier for controlling the timing of when the sense amplifier is enabled in relation to the memory array addressing by generating a plurality of delayed versions of the sense amplifier enable signal and coupling one of the delayed versions of the sense amplifier enable signal to the sense amplifier in response to a control signal. By multiplexing multiple delayed versions of the sense amplifier enable signal under control of programmable delay selection logic, an optional delay is provided to make enable the sense amplifier more quickly or more slowly in reference to a memory array signal, depending upon control signal inputs to the selection logic.

US Patent:

6999372, Feb 14, 2006

Filed:

Mar 18, 2003

Appl. No.:

10/391278

Inventors:

Toshinari Takayanagi - San Jose CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G11C 8/00
G11C 11/00

US Classification:

36523005, 365154, 365156

Abstract:

A multi-port semiconductor memory device is provided with current limiting transistor devices interposed between the memory cell and the bit line transfer gates for multiple bit line pairs. Where each bit line pair represents a memory port that is connected to the memory cell during read and write operations, the current limiting transistor devices effectively reduce the current flow from non-writing bit lines, thereby improving memory writability. In addition, the current limiting transistor devices effectively reduce the current flow to non-reading bit lines, thereby improving memory stability.

US Patent:

7177201, Feb 13, 2007

Filed:

Sep 17, 2003

Appl. No.:

10/664104

Inventors:

Toshinari Takayanagi - San Jose CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G11C 7/00

US Classification:

36518901, 365163, 365196

Abstract:

An accumulated data-dependent post-manufacture shift in a characteristic of one or more of a pair of matched devices within an integrated circuit may cause a mismatch in the characteristic between the pair of matched devices. This mismatch may be reduced by preconditioning the matched devices to cause an initial shift in the characteristic in each of the matched devices and to thereby reduce an expected magnitude of any further lifetime shift in the characteristic of either matched device. In an exemplary sense amplifier circuit having matched cross-coupled PMOS load devices, a data dependent threshold mismatch between the PMOS devices resulting from a Negative Bias Temperature Instability (NBTI) effect may be reduced by biasing both of the matched PMOS devices so that both experience an initial NBTI Vt shift, and so that any expected further Vt shift in either device over the product lifetime is reduced. Consequently the amount of threshold mismatch that may subsequently develop over the product lifetime is likewise reduced.

US Patent:

7254795, Aug 7, 2007

Filed:

Jun 15, 2005

Appl. No.:

11/152929

Inventors:

Umesh Nair - Newark CA, US
Toshinari Takayanagi - Sunnyvale CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 6, 716 2, 716 10

Abstract:

A method for optimizing low threshold-voltage (V) devices in an integrated circuit design. The method includes identifying paths and nodes within the integrated circuit design, determining node overlap within the integrated circuit design, calculating possible solutions for addressing timing violations within the integrated circuit design, choosing a solution for addressing timing violations, inserting low Vdevices at particular nodes of the integrated circuit design, and repeating the calculated possible solutions wherein choosing a solution and inserting low Vdevices at particular nodes to address timing violations within the integrated circuit design.

US Patent:

7328416, Feb 5, 2008

Filed:

Jan 24, 2005

Appl. No.:

11/042043

Inventors:

Ming Yin - Hayward CA, US
Toshinari Takayanagi - San Jose CA, US
Alan Smith - Santa Clara CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 6, 716 10, 716 13, 703 16

Abstract:

A method is provided for modeling timing characteristics of a circuit block of an integrated circuit, which includes a main circuit and a timing circuit. The method comprises determining an output pin output delay and determining a timing circuit delay. The output pin output delay is an interval of time from a clock signal reaching a clock reference point (CRP) to an output signal arriving at the output pin. The clock reference point is positioned between the timing circuit and the main circuit. The timing circuit delay is an interval of time from a clock signal arriving at a clock input pin to a clock signal arriving at the CRP. The determination of the timing circuit delay is based on a computer simulation of a netlist of circuit elements in the timing circuit.

US Patent:

8013669, Sep 6, 2011

Filed:

Oct 27, 2009

Appl. No.:

12/606534

Inventors:

Shingo Suzuki - San Jose CA, US
Toshinari Takayanagi - San Jose CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G05F 1/10

US Classification:

327544, 713340

Abstract:

An apparatus and method for detecting noise in a power supply voltage. A circuit may include a voltage generation unit coupled to receive a power supply voltage, and a detection unit. The voltage generation unit may generate first and second voltages using the power supply voltage, and may vary the relationship therebetween responsive to fluctuations in the power supply voltage. A detection unit may detect the variations in the relationship between the first and second voltages that result from fluctuations in the power supply voltage. Responsive to detecting the variations, the detection unit may generate pulses to be provided to a counter. The counter may update a count value responsive to receiving pulses.

US Patent:

8026741, Sep 27, 2011

Filed:

Jul 31, 2009

Appl. No.:

12/533320

Inventors:

Toshinari Takayanagi - San Jose CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

H03K 19/094
H03K 3/00
H03B 1/00

US Classification:

326 83, 326 80, 327108

Abstract:

CMOS circuitry having mixed threshold voltages is disclosed. Circuits may be implemented using PMOS transistors, NMOS transistors, or both. For at least one given type of transistor (PMOS or NMOS), a circuit includes at least one transistor configured to switch at a first nominal threshold voltage and at least one transistor configured to switch at a second nominal threshold voltage. The different threshold voltages among a given transistor type are realized by varying the thickness of the transistor gate oxides and/or the channel dopant density, for example.

US Patent:

8120208, Feb 21, 2012

Filed:

Jun 15, 2009

Appl. No.:

12/484692

Inventors:

Toshinari Takayanagi - San Jose CA, US
Shingo Suzuki - San Jose CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G05F 1/10

US Classification:

307113, 307112

Abstract:

In one embodiment, a power gated circuit block includes power switches that couple at least one of the power supply grids within the block to the global power supply grids of the integrated circuit. The power switches receive an enable that indicates whether or not the power gated block is enabled or disabled. If the power gated block is enabled, the power switches are turned on and electrically connect the global power supply grid with the internal (or local) power supply grid; otherwise the power switches electrically isolate the local power supply grid from the global power supply grid. The power switches are physically distributed over an area occupied by the power gated block, including near an edge of the area. The number of power switches near the edge is greater than the number of switches included at other locations in the area to provide a worst case impedance experienced at points throughout the area that is approximately equal.