Vadim Khmelnitsky from 1041 Foster City Blvd, San Mateo, CA 94404, age 53, Phone: 6503413571

Resumes

Technical Team Lead

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Location:

San Francisco, CA

Industry:

Computer Software

Work:

Sandisk
Technical Team Lead

Skills:

Nand
Hid
Firmware

Us Patents

Multipage Preparation Commands For Non-Volatile Memory Systems
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US Patent:

8321647, Nov 27, 2012
Filed:

Aug 20, 2009
Appl. No.:

12/545011
Inventors:

Vadim Khmelnitsky - Foster City CA, US
Nir Jacob Wakrat - Los Altos CA, US
Tahoma Toelkes - San Jose CA, US
Daniel Jeffrey Post - Campbell CA, US
Anthony Fai - Palo Alto CA, US
Assignee:

Apple Inc. - Cupertino CA
International Classification:

G06F 13/00
G06F 13/28
US Classification:

711170, 711154, 711E12002
Abstract:

Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation.

Detecting Corrupted Data For A System Having Non-Volatile Memory
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US Patent:

8341500, Dec 25, 2012
Filed:

Aug 31, 2010
Appl. No.:

12/872884
Inventors:

Matthew Byom - Campbell CA, US
Daniel J. Post - Cupertino CA, US
Vadim Khmelnitsky - Foster City CA, US
Nir J. Wakrat - Los Altos CA, US
Assignee:

Apple Inc. - Cupertino CA
International Classification:

G11C 29/00
US Classification:

714773, 714763, 36518533, 375286
Abstract:

Systems, apparatuses, and methods are provided for detecting corrupted data for a system having non-volatile memory, such as NAND Flash memory. In some embodiments, a non-volatile memory (“NVM”) package is provided, which can include a NVM controller and one or more NVM dies. Each NVM die can include one or more blocks, where each block can further include an array of memory cells. One or more of these memory cells can be configured as “multi-level cells” (“MLCs”). In some embodiments, in order to avoid transmitting data obtained from an improperly programmed page of a MLC, a NVM controller can be configured to detect if data obtained from the page is in fact data stored in a different page.

Data Storage Scheme For Non-Volatile Memories Based On Data Priority
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US Patent:

8356137, Jan 15, 2013
Filed:

Feb 26, 2010
Appl. No.:

12/713529
Inventors:

Daniel J. Post - Campbell CA, US
Matthew Byom - Campbell CA, US
Vadim Khmelnitsky - Foster City CA, US
Nir J. Wakrat - Los Altos CA, US
Kenneth Herman - San Jose CA, US
Assignee:

Apple Inc. - Cupertino CA
International Classification:

G06F 12/06
G11C 20/00
US Classification:

711103, 711158, 714763, 714768, 714773
Abstract:

Systems and methods are disclosed for partitioning data for storage in a non-volatile memory (“NVM”), such as flash memory. In some embodiments, a priority may be assigned to data being stored, and the data may be logically partitioned based on the priority. For example, a file system may identify a logical address within a first predetermined range for higher priority data and within a second predetermined range for lower priority data, such using a union file system. Using the logical address, a NVM driver can determine the priority of data being stored and can process (e. g. , encode) the data based on the priority. The NVM driver can store an identifier in the NVM along with the data, and the identifier can indicate the processing techniques used on the associated data.

Architecture For Address Mapping Of Managed Non-Volatile Memory
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US Patent:

8370603, Feb 5, 2013
Filed:

Nov 6, 2009
Appl. No.:

12/614369
Inventors:

Tahoma Toelkes - San Jose CA, US
Nir Jacob Wakrat - Los Altos CA, US
Kenneth L. Herman - San Jose CA, US
Barry Corlett - Brisbane CA, US
Vadim Khmelnitsky - Foster City CA, US
Anthony Fai - Palo Alto CA, US
Daniel Jeffrey Post - Campbell CA, US
Hsiao Thio - San Jose CA, US
Assignee:

Apple Inc. - Cupertino CA
International Classification:

G06F 12/00
G06F 13/00
G06F 13/28
G06F 9/34
G06F 9/26
US Classification:

711202, 711103
Abstract:

The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.

Memory Mapping Restore And Garbage Collection Operations
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US Patent:

8397014, Mar 12, 2013
Filed:

Aug 18, 2008
Appl. No.:

12/193613
Inventors:

Vadim Khmelnitsky - Foster City CA, US
Nir Jacob Wakrat - San Jose CA, US
Assignee:

Apple Inc. - Cupertino CA
International Classification:

G06F 13/10
US Classification:

711103
Abstract:

Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the physical address of the first lookup table in non-volatile memory. In some implementations, a cache in volatile memory holds the physical addresses of the most recently written logical sectors. Also disclosed is a block TOC describing block content which can be used for garbage collection and restore operations.

Selective Retirement Of Blocks
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US Patent:

8411519, Apr 2, 2013
Filed:

Jul 23, 2010
Appl. No.:

12/842477
Inventors:

Matthew Byom - Campbell CA, US
Daniel J. Post - Campbell CA, US
Vadim Khmelnitsky - Foster City CA, US
Assignee:

Apple Inc. - Cupertino CA
International Classification:

G11C 29/00
US Classification:

365200, 36523003, 714 42, 714718
Abstract:

Systems and methods are provided for selectively retiring blocks based on refresh events of those blocks. In addition to refresh events, other criteria may be applied in making a decision whether to retire a block. By applying the criteria, the system is able to selectively retire blocks that may otherwise continue to be refreshed.

Memory Mapping Techniques
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US Patent:

8417893, Apr 9, 2013
Filed:

Aug 18, 2008
Appl. No.:

12/193528
Inventors:

Vadim Khmelnitsky - Foster City CA, US
Nir Jacob Wakrat - Santa Clara CA, US
Assignee:

Apple Inc. - Cupertino CA
International Classification:

G06F 12/00
G06F 13/00
US Classification:

711135, 711202, 711206, 711207
Abstract:

Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the physical address of the first lookup table in non-volatile memory. In some implementations, a cache in volatile memory holds the physical addresses of the most recently written logical sectors. Also disclosed is a block TOC describing block content which can be used for garbage collection and restore operations.

Low Latency Read Operation For Managed Non-Volatile Memory
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US Patent:

8438453, May 7, 2013
Filed:

Aug 7, 2009
Appl. No.:

12/538053
Inventors:

Daniel Jeffrey Post - Campbell CA, US
Nir Jacob Wakrat - Los Altos CA, US
Vadim Khmelnitsky - Foster City CA, US
Assignee:

Apple Inc. - Cupertino CA
International Classification:

G11C 29/00
US Classification:

714763
Abstract:

In a memory system, a host controller is coupled to a non-volatile memory (NVM) package (e. g. , NAND device). The host controller sends a read command to the NVM package requesting a low latency read operation. Responsive to the read command, a controller in the NVM package retrieves the data and sends the data to an ECC engine for correcting. Following the read command, the host controller sends a read status request command to the controller in the NVM package. Responsive to the read status request, the controller sends a status report to the host controller indicating that some or all of the data is available for transfer to the host controller. Responsive to the report, the host controller transfers the data. An underrun status can be determined to indicate that uncorrected data had been transferred to the host controller.