Vinod Kumar Kathail from 4155 King Arthur Ct, Palo Alto, CA 94306, age 68, Phone: 6508567939

Us Patents

Auto Design Of Vliw Processors
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US Patent:

6385757, May 7, 2002
Filed:

Aug 20, 1999
Appl. No.:

09/378395
Inventors:

Shail Aditya Gupta - Sunnyvale CA
B. Ramakrishna Rau - Los Altos CA
Vinod K. Kathail - Cupertino CA
Michael S. Schlansker - Los Altos CA
Assignee:

Hewlett-Packard Company - Palo Alto CA
International Classification:

G06F 1750
US Classification:

716 1
Abstract:

A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.

Automated Design Of Processor Systems Using Feedback From Internal Measurements Of Candidate Systems
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US Patent:

6408428, Jun 18, 2002
Filed:

Aug 20, 1999
Appl. No.:

09/378290
Inventors:

Michael S. Schlansker - Los Altos CA
Vinod K. Kathail - Cupertino CA
Greg Snider - Campbell CA
Shail Aditya Gupta - Sunnyvale CA
Scott A. Mahlke - Mountain View CA
Santosh Abraham - Pleasanton CA
Assignee:

Hewlett-Packard Company - Palo Alto CA
International Classification:

G06F 1750
US Classification:

716 17, 716 18
Abstract:

An automated design system for VLIW processors explores a parameterized design space to assist in identifying candidate processor designs that satisfy desired design constraints, such as processor cost and performance. A VLIW synthesis process takes as input a specification of processor parameters and synthesizes a datapath specification, an instruction format design, and a control path specification. The synthesis process also extracts a machine description suitable to re-target a compiler. The re-targeted compiler generates operation issue statistics for an application program or set of programs. Using these statistics, a procedure for searching the design space can extract internal resources utilization information that is used to determine new candidate processors for evaluation.

Programmatic Synthesis Of Processor Element Arrays
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US Patent:

6507947, Jan 14, 2003
Filed:

Aug 20, 1999
Appl. No.:

09/378298
Inventors:

Robert S. Schreiber - Palo Alto CA
B. Ramakrishna Rau - Los Altos CA
Shail Aditya Gupta - Sunnyvale CA
Vinod K. Kathail - Cupertino CA
Sadun Anik - Akatlar, TR
Assignee:

Hewlett-Packard Company - Palo Alto CA
International Classification:

G06F 945
US Classification:

717160, 717159, 717161
Abstract:

A programmatic method transforms a nested loop in a high level programming language into a set of parallel processes, each a single time loop, such that the parallel processes satisfy a specified design constraint. Another programmatic method synthesizes a processor array from the set of parallel processes and a specified design constraint.

Automatic Design Of Vliw Processors
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US Patent:

6581187, Jun 17, 2003
Filed:

Feb 6, 2002
Appl. No.:

10/068723
Inventors:

Shail Aditya Gupta - Sunnyvale CA
B. Ramakrishna Rau - Los Altos CA
Vinod K. Kathail - Cupertino CA
Michael S. Schlansker - Los Altos CA
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

G06F 1750
US Classification:

716 1
Abstract:

A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.

Automatic Design Of Vliw Processors
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US Patent:

6651222, Nov 18, 2003
Filed:

Feb 6, 2002
Appl. No.:

10/068216
Inventors:

Shail Aditya Gupta - Sunnyvale CA
B. Ramakrishna Rau - Los Altos CA
Vinod K. Kathail - Cupertino CA
Michael S. Schlansker - Los Altos CA
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

G06F 1750
US Classification:

716 1, 716 2, 716 3
Abstract:

A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.

Storage System For Use In Custom Loop Accelerators And The Like
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US Patent:

6766445, Jul 20, 2004
Filed:

Mar 23, 2001
Appl. No.:

09/816851
Inventors:

Michael Steven Schlansker - Los Altos CA
Vinod Kumar Kathail - Cupertino CA
Shail Aditya Gupta - Sunnyvale CA
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

G06F 940
US Classification:

712241
Abstract:

A computational unit for use in loop computations. The computational unit includes a function unit, a plurality of phase lines, and a storage register. The computational unit is programmed to initiate one iteration of the loop every II cycles. Each function unit has a result output for outputting one computational result each cycle. There is one phase line corresponding to each of the II cycles. The storage register includes a linear connected array of shift cells having a first shift cell. Each shift cell has an input port, an output port, a shift control port, and an OR gate. Each shift cell receives the value to be stored in the shift cell on the input port, the stored value being stored in response to a control signal on the shift control port. The OR gate has an output connected to the shift enable port and one input for each cycle on which that shift cell is to receive the control signal, that input being connected to the phase line corresponding to that cycle. The input port of the first shift cell is connected to the result output.

Retargetable Computer Design System
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US Patent:

6772106, Aug 3, 2004
Filed:

Aug 20, 1999
Appl. No.:

09/378580
Inventors:

Scott A. Mahlke - Mountain View CA
Santosh G. Abraham - Pleasanton CA
Vinod K. Kathail - Cupertino CA
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

G06F 944
US Classification:

703 21, 703 22, 717128
Abstract:

An automatic and retargetable computer design system is using a combination of simulation and performance prediction to investigate a plurality of target computer systems. A high-level specification and a predetermined application are used by the computer design system to provide inputs into a computer evaluator. The computer evaluator has reference computer system dependent and independent systems for producing a reference representation and dynamic behavior information, respectively, of the application. The reference representation and information are mated to produce further information to drive a simulator. The simulator provides performance information of a reference computer system. The performance information is provided to another computer evaluator, which has a target computer system dependent system for producing a target representation of the application for the plurality of target computer systems. The performance information and the target representation are used by a computer system predictor for quickly estimating the performance information of the plurality of target computer systems in a simulation efficient manner.

Method And System For The Design Of Pipelines Of Processors
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US Patent:

7107199, Sep 12, 2006
Filed:

Oct 31, 2002
Appl. No.:

10/284932
Inventors:

Robert S. Schreiber - Pal Alto CA, US
Shail Aditya Gupta - Sunnyvale CA, US
Vinod K. Kathail - Palo Alto CA, US
Santosh George Abraham - Pleasanton CA, US
Bantwal Ramakrishna Rau - Los Altos CA, US
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

G06F 17/50
US Classification:

703 13
Abstract:

A method of designing a pipeline comprises the steps of: accepting a task procedure expressed in a standard programming language, the task procedure including a sequence of computational steps; accepting a performance requirement of the pipeline; and automatically creating a hardware description of the pipeline, the pipeline comprising a plurality of interconnected processor stages, each of the processor stages for performing a respective one of the computational steps, the pipeline having characteristics consistent with the performance requirement of the pipeline.